Specifications

Programmers Model
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-7
ID052914 Non-Confidential
Note
• The actual address for the peripheral depends on the chip select mapping in the static
memory controller in the CoreTile Express or LogicTile Express daughterboard. See the
documentation for the daughterboard.
• The daughterboards typically have additional peripherals. See the documentation for the
daughterboard.
Reserved - CS3 0x00150000 - 0x0015FFFF
Serial Bus DVI Custom CS3 0x00160000 - 0x0016FFFF
RTC ARM PL031 CS3 0x00170000 - 0x0017FFFF
Reserved - CS3 0x00180000 - 0x0018FFFF
Reserved - CS3 0x00190000 - 0x0019FFFF
Compact Flash Custom CS3 0x001A0000 - 0x001AFFFF
UART4 ARM PL011 CS3 0x001B0000 - 0x001BFFFF
Reserved - CS3 0x001C0000 - 0x001CFFFF
Reserved - CS3 0x001D0000 - 0x001DFFFF
Reserved - CS3 0x001E0000 - 0x001EFFFF
CLCD control ARM PL111 CS3 0x001F0000 - 0x001FFFFF
Reserved - CS3 0x00200000 - 0x03FFFFFF
Table 4-2 Motherboard peripheral ARM Cortex-A Series memory map (continued)
Peripheral Interface logic SMB chip select Address offset