Specifications

Hardware Description
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2.6 Interrupt signals
There is no interrupt controller on the motherboard. The IO FPGA peripheral interrupts can
connect to an interrupt controller in a CoreTile Express daughterboard through the SB bus.
The IO FPGA also generates CPUIRQ, CPUFIQ, and nEvent for use by legacy cores that do
not have a GIC interrupt controller.
The IO FPGA peripheral interrupts also connect to the daughterboard Site 2 and enable a core
and interrupt controller implemented in the daughterboard FPGA to process interrupts.
You can generate the four interrupt signals INT[3:0] by the daughterboards and are input to the
IO FPGA. These are returned to the daughterboards on signals IRQ[39:36] and IRQ[35:32].
The function of these is determined by the daughterboard.
Figure 2-8 shows the interrupt architecture.
Figure 2-8 Interrupt architecture
For more information on interrupt handling, see the documentation for your CoreTile Express
daughterboard.
Table 2-2 shows the interrupt mapping for the IRQ[47:0] signals.
Motherboard Express μATX
LogicTile Express daughterboard
(in Site 2)
CoreTile Express daughterboard
(in Site 1)
HDRY
Test
chip
HDRY1 HDRY2
IO FPGA
SB1
SB _INT[3:0]
SB_nEvent
HDRY
FPGA
SB2_INT[3:0]
SB_IRQ[47:0]
SB_nCPUIRQ
SB_nCPUFIQ
SB_nEvent
SB1_INT[3:0]
SB_nCPUIRQ
SB_nCPUFIQ
SB_IRQ[47:0]
SB2
SB _INT[3:0]
SB_nEvent
SB_nCPUIRQ
SB_nCPUFIQ
SB_IRQ[47:0]
Table 2-2 Interrupt signals
SB_IRQ[ ] interrupt Interrupt signal Description
0 WDOG0INT Watchdog timer
1 SWINT Software interrupt, see Miscellaneous Flags Register on page 4-16
2 TIM01INT Timer interrupt
3 TIM23INT Timer interrupt