Specifications

Hardware Description
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-9
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2.3 Clock architecture
Table 2-1 shows the motherboard clock sources.
On power up, the MCC sets OSC[5:0] to the values specified in the
board.txt configuration file
in the USBMSD. See the ARM
®
Versatile
™
Express Configuration Technical Reference Manual.
The daughterboards have their own clock generators that are independent of the motherboard
clocks. These clocks are set by the values in the
board.txt file for the daughterboards. See the
documentation supplied with your daughterboard.
Caution
Ensure that the clock settings are within the permitted range.
You can configure the motherboard OSC clocks in the following ways:
1. By editing the
board.txt file. ARM recommends that you perform this method first.
2. By using of the
CFG W command from the DEBUG submenu of the MCC command line
in run mode. See the ARM
®
Versatile
™
Express Configuration Technical Reference
Manual.
3. By writing application code to the SYS_CFG registers. See System Configuration
registers on page 4-21 and the pseudo code Example 4-1 on page 4-24.
4. By using the CONFIGURE submenu from the Boot Monitor command line.
Methods 2, 3, and 4 permit clock switching in run mode. Method 1 requires a reset to become
effective.
Figure 2-3 on page 2-10 shows an overview of the clocks in a typical Versatile Express system.
Table 2-1 Motherboard clocks
Oscillator Default Description Range
OSC0 50MHz MCC static memory clock. The MCC uses this clock for accesses to the SMB
before control of the SMB buses is passed to the daughterboards.
After configuration, each daughterboard outputs its own SMB clock to the IO
FPGA. In run mode, the SMB clock is switched to the daughterboards and the IO
FPGA returns the delayed SMB clocks to the daughterboards. This enables the
daughterboard memory controllers to adjust the frequency for optimum
operation.
25MHz-60MHz
OSC1 23.75MHz CLCD clock to the IO FPGA. 23.75MHz-63.5MHz
OSC2 24MHz IO FPGA peripheral clock. This is the reference clock for peripherals such as, for
example, the UARTs.
This clock is used directly by the peripheral or as the reference to a clock
generator in the peripheral.
24MHz
OSC3 24MHz IO FPGA. Reserved. 2MHz-230MHz
OSC4 24MHz System bus global clock. A divide by two block inside the MUX FPGA derives
the 12MHz system bus global clock. This drives the attached CoreTile and
LogicTile daughterboards. See Figure 2-3 on page 2-10.
2MHz-230MHz
OSC5 24MHz IO FPGA. Reserved. 2MHz-230MHz
PCI-E - A dedicated PCI-Express clock generator provides the clocks to the PCI-Express
slots and the daughterboards. You cannot configure this clock.
100MHz