Specifications

Hardware Description

ID052914 Non-Confidential

2.1.1 Motherboard buses

The motherboard architecture uses the following buses:

• Configuration Bus

• Static Memory Bus

• System Bus

• MultiMedia Bus

• High-Speed Bus on page 2-5

• PCIe Bus on page 2-5.

Figure 2-1 on page 2-2 shows how these buses interconnect.

Configuration Bus

The Motherboard Configuration Controller (MCC) and Daughterboard Configuration

Controller use the Configuration Bus (CB) to determine the functionality and capabilities of the

daughterboards before powering up and releasing the resets. This minimizes the chance of

damage to the boards. The CB controls the power and reset sequence. It also updates the FPGA

images and software on the daughterboards.

Static Memory Bus

The underlying architecture uses the Static Memory Bus (SMB) for all peripheral and memory

accesses from the daughterboards to the motherboard. A Static Memory Controller in the

daughterboard outputs chip select signals to access memory and peripherals on the

motherboard. The memory controller determines the base address for each chip select. See IO

Peripherals and interfaces on page 4-26.

Note

• Site 2 has limited access to the motherboard.

• Site 2 can only access the motherboard using chip select nCS7, peripherals, and nCS3,

Video SRAM only.

System Bus

The System Bus connects interrupts and DMAs:

• From the motherboard peripherals to the daughterboards.

• Between the daughterboards.

MultiMedia Bus

The MultiMedia Bus (MMB) enables the motherboard or either daughterboard to drive audio

and video data to the DVI connector. A dedicated FPGA manages multiplexing the sources and

driving the outputs to the HDMI transmitter.

The motherboard supports:

• Video with 25 to 165MHz pixel clock, DTV 480p to 1080p, or PC 640x480 to 1600x1200,

VGA to UXGA

• Audio S/PDIF interface with 2 channels at 192kHz or I2S interface with eight channels at

96kHz.