ARM Motherboard Express µATX ® V2M-P1 Technical Reference Manual Copyright © 2009-2014, ARM. All rights reserved.
ARM Motherboard Express µATX Technical Reference Manual Copyright © 2009-2014, ARM. All rights reserved.
Conformance Notices This section contains conformance notices. Federal Communications Commission Notice This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c). CE Declaration of Conformity The system should be powered down when not in use. The Motherboard Express µATX generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications.
Contents ARM Motherboard Express µATX Technical Reference Manual Preface About this book .......................................................................................................... vii Feedback .................................................................................................................... xi Chapter 1 Introduction 1.1 1.2 Chapter 2 Hardware Description 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Chapter 3 Configuration environment ..............................................
4.5 Appendix A Signal Descriptions A.1 A.2 Appendix B ARM DUI 0447J ID052914 Audio CODEC interface ........................................................................................... A-2 UART interface ........................................................................................................ A-3 Specifications B.1 B.2 Appendix C IO Peripherals and interfaces ................................................................................ 4-26 Timing specifications ............
Preface This Technical Reference Manual (TRM) is for the Motherboard Express µATX. It contains the following sections: • About this book on page vii • Feedback on page xi. ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM. All rights reserved.
Preface About this book This book describes how to set up and use the Motherboard Express µAdvanced Technology Extended (ATX). The Motherboard Express µATX is part of the Versatile™ Express family of boards that includes the ARM® CoreTile Express and ARM® LogicTile Express daughterboards. Product revision status The rnpn identifier indicates the revision status of the product described in this book, where: rn Identifies the major revision of the product.
Preface Typographical Conventions Conventions that this book can use are described in: • Typographical • Timing diagrams • Signals on page ix. Typographical The typographical conventions are: italic Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.
Preface Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and they look similar to the bus change shown in Key to timing diagram conventions on page viii. If a timing diagram shows a single-bit signal in this way then its value does not affect the accompanying description. Signals The signal conventions are: Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means: • HIGH for active-HIGH signals.
Preface The following publications provide information about related ARM products and toolkits: • ARM® CoreTile Express A9x4 Technical Reference Manual (ARM DUI 0448) • ARM® CoreTile Express A5x2 Technical Reference Manual (ARM DUI 0541) • ARM® CoreTile Express A15x2 Technical Reference Manual (ARM DUI 0604) • ARM® CoreTile Express A15x2 A7x3 Technical Reference Manual (ARM DDI 0503) • ARM® LogicTile Express 3MG Technical Reference Manual (ARM DUI 0449) • ARM® LogicTile Express 13MG Technical Re
Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version. • An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. Feedback on content If you have comments on content then send an e-mail to errata@arm.com.
Chapter 1 Introduction This chapter introduces the Motherboard Express µATX. It contains the following sections: • About the Motherboard Express µATX on page 1-2 • Precautions on page 1-5. ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM. All rights reserved.
Introduction 1.1 About the Motherboard Express µATX The Motherboard Express µATX is the basis for a highly integrated software and hardware development system based on the ARM SMP architecture. The motherboard provides the following features: • Peripherals for multimedia or networking environments. • All motherboard peripherals and functions are accessed through a static memory bus to simplify access from daughterboards. • High-performance PCI-Express slots for expansion cards.
Introduction PCI Express slots Debug JTAG (to Core Tile Express) Back panel connectors Case fan (12V) User LEDs D0 D7 Manufacturing Test USB status LEDs OTGON USB2ON USB3ON Test (ILA) ILA Voltage status LEDs 5VOK 3.3VOK SB Micro SDCard (configuration memory) Battery (MCC RTCC) CoreTile Express LogicTile Express daughterboard daughterboard ATX PSU connector (with plug from enclosure connector) Figure 1-1 Motherboard layout ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM.
Introduction 1.1.1 Back panel connectors Figure 1-2 shows the ATX rear panel that provides: • Power supply connector. • Keyboard and mouse interface, PS/2. • Ethernet interface. • Two USB 2.0 ports. • One USB OTG port. • USB-B device connector for loading configuration files. • Audio interface, containing analog microphone-in, line-in, and line-out. • Four RS232 serial ports. • Video interface, DVI-I supports analog and digital, and digital audio. • JTAG connector, to CoreTile Express JTAG connector.
Introduction 1.2 Precautions This section contains safety information and advice on how to avoid damage to the motherboard. 1.2.1 Ensuring safety The motherboard is powered from an ATX power supply unit within the ATX enclosure. Warning To avoid a safety hazard: 1.2.2 • To use the motherboard in its supplied plastic enclosure, only use the supplied 12V power supply unit to provide power to the connector on the enclosure.
Chapter 2 Hardware Description This chapter describes the hardware on the Motherboard Express µATX. It contains the following sections: • Motherboard architecture and buses on page 2-2 • Power up, on/off and reset signals on page 2-6 • Clock architecture on page 2-9 • Power on page 2-11 • Peripherals and interfaces on the motherboard on page 2-12 • Interrupt signals on page 2-18 • DMA signals on page 2-20 • JTAG and test connectors on page 2-21. ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM.
Hardware Description 2.1 Motherboard architecture and buses Figure 2-1 shows a motherboard with attached Tile Express and LogicTile Express daughterboards.
Hardware Description ARM DUI 0447J ID052914 • High-speed bus interconnect between daughterboards with support for Low-Voltage Differential Signalling (LVDS). • Bus interfaces between motherboard and daughterboards for PCIe, Static Memory, MultiMedia, and System Bus, interrupts. • Power circuitry with (VIO) voltage from 0.8V-3.3V to enable interfacing with a wide range of devices. • Four PCI Express Gen 1 slots, each supporting four lanes. • MMC/SD card slot. • Compact Flash slot.
Hardware Description 2.1.1 Motherboard buses The motherboard architecture uses the following buses: • Configuration Bus • Static Memory Bus • System Bus • MultiMedia Bus • High-Speed Bus on page 2-5 • PCIe Bus on page 2-5. Figure 2-1 on page 2-2 shows how these buses interconnect.
Hardware Description High-Speed Bus The motherboard connects the two daughterboards with two High-Speed Buses (HSB). The bus interconnect can provide up to: • 360 single-ended signals. • 160 Low Voltage Differential Signalling (LVDS) signal pairs. • • Note The HSB typically implements a multiplexed AXI bus. There is no connection from the HSB to devices on the motherboard. See the documentation for your daughterboard.
Hardware Description 2.2 Power up, on/off and reset signals You can use either of the push buttons to reset the system, but only the ON/OFF push button can power up the system. The motherboard drives two reset signals to each daughterboard and receives a reset-request signal from each daughterboard. Figure 2-2 shows the power up ON/OFF/Soft Reset push button and Hardware RESET push-button signals in the system.
Hardware Description 2.2.1 Power up reset A full system configuration is performed at power up. See the ARM® Versatile™ Express Configuration Technical Reference Manual. 2.2.2 ON/OFF/Soft Reset push button briefly pressed You can reset the system by briefly pressing the ON/OFF/Soft Reset switch on the back panel. This performs a software reset of the ARM test chip on the CoreTile daughterboard.
Hardware Description 2.2.4 External reset requests from the daughterboards Either daughterboard can issue an external reset request to the motherboard: 1. An external reset is received from the JTAG connector, nSRST, on the CoreTile Express daughterboard. 2. The Daughterboard Configuration Controller asserts CB_RSTREQ to the MCC on the motherboard. See Figure 2-2 on page 2-6. 3. The MCC asserts the CB_nRST reset signal. Depending on the setting of ASSERTNPOR in the generic configuration file config.
Hardware Description 2.3 Clock architecture Table 2-1 shows the motherboard clock sources. Table 2-1 Motherboard clocks Oscillator Default Description Range OSC0 50MHz MCC static memory clock. The MCC uses this clock for accesses to the SMB before control of the SMB buses is passed to the daughterboards. After configuration, each daughterboard outputs its own SMB clock to the IO FPGA.
Hardware Description CoreTile Express daughterboard (Site 1) Test chip TC reference clock CLCD clock Clock generators SB_GCLK External AXIS clock PCI reference clock LogicTile Express daughterboard (Site 2) FPGA PCI reference clock MMB clocks MMB clocks SMB clock SMB feedback SB_GCLK SMB clock SMB feedback External AXIM clock Daughterboard Configuration Controller Clock generators FPGA reference clocks HSB (S) AXI clock logic M S Daughterboard Configuration Controller HDRY HDRX HDRX HDRY
Hardware Description 2.4 Power Power to the board is provided by either: An external 12V power supply The output goes to the power connector on the back panel. The 12V, 5A, supply from the back-panel connector goes through an adaptor and connects to the ATX connector on the motherboard. An ATX power supply The output goes to the ATX power connector on the motherboard. The ATX supply is required for PCI-Express cards.
Hardware Description 2.5 Peripherals and interfaces on the motherboard This section introduces the peripherals and interfaces located on the motherboard. It contains the following: • IO FPGA peripherals • Ethernet on page 2-14 • USB on page 2-14 • DVI multiplexer on page 2-15 • PCI-Express on page 2-15. For more information about the programming interface to the IO peripherals and interfaces, see IO Peripherals and interfaces on page 4-26. 2.5.
Hardware Description UARTs Four UARTs are implemented with PL011 PrimeCells incorporated into the baseboard FPGA. See UART on page 4-37. User Switches and LEDs You can access the two physical user switches, SW[1] and SW[2], and eight user LEDs on the motherboard from your applications. • SW[1] is normally used to run the Boot Monitor boot script. • SW[2] is a hardware enable switch for remote UART0 control. SW[2] is not normally used by your application.
Hardware Description Site 1 Site 2 CB SMB1 to Site 1 Motherboard Configuration Controller SB_GCLK SMB2 to Site 2 Site 1 Site 2 MMB1 to Site 1 Interrupts and DMA control MMB2 to Site 2 Matrix, multiplexers, and bridges NOR FLASH 0 CS0 NOR FLASH 1 CS4 User SRAM CS1 Ethernet CS2 USB CS2 Video SRAM CS2 MMB MMB Mux DVI AACI Peripherals Compact Flash 2 x KMI CS3 SD/MMC 4 x UART User LEDS PCIe I2C I/O FPGA Figure 2-5 Architectural block diagram of IO FPGA using the ARM Cortex-A Series
Hardware Description 2.5.4 DVI multiplexer The motherboard has a Digital Visual Interface (DVI) connector. A multiplexer on the motherboard selects the source for the video output as either the: • MMB bus from the CoreTile Express daughterboard in Site 1. • MMB bus from the LogicTile Express daughterboard in Site 2. • CLCD controller in the motherboard IO FPGA. The source for the DVI is determined by the generic motherboard configuration file.
Hardware Description These are connected through a IDT89PES32H8 PCI Express switch to the PCIe buses from the two daughterboards. You can configure the PCIe switch to work with CoreTile Express or LogicTile Express daughterboards configured as an integrated PCI-Express root complex. Note The V2M-P1 motherboard supports a root complex either on the daughterboard in Site 1 or on the daughterboard in Site 2. You select which site contains the root complex by editing the config.txt file.
Hardware Description Site 1 Site 2 CoreTile Express daughterboard LogicTile Express daughterboard Test chip with End Point or Root Complex FPGA with End Point or Root Complex HDRY HDRY SMB2 PCIe2 SMB1 PCIe1 HDRY1 HDRY2 x4 x8 x8 PCI-Express Switch 32 lanes 6 ports x4 x4 I2C Reset and configuration logic Motherboard Express μATX Motherboard Configuration Controller (MCC) Slot x4, 4 lanes Serial bus interface Slot x 4, 4 lanes IO FPGA Slot x 8, 4 lanes PCI-Express slot x16, 4 lanes x4
Hardware Description 2.6 Interrupt signals There is no interrupt controller on the motherboard. The IO FPGA peripheral interrupts can connect to an interrupt controller in a CoreTile Express daughterboard through the SB bus. The IO FPGA also generates CPUIRQ, CPUFIQ, and nEvent for use by legacy cores that do not have a GIC interrupt controller.
Hardware Description Table 2-2 Interrupt signals (continued) ARM DUI 0447J ID052914 SB_IRQ[ ] interrupt Interrupt signal Description 4 RTCINTR Timer interrupt 5 UART0INTR UART interrupt 6 UART1INTR UART interrupt 7 UART2INTR UART interrupt 8 UART3INTR UART interrupt 9 MCI_INTR[0] MultiMedia card interrupt 10 MCI_INTR[1] MultiMedia card interrupt 11 AACI_INTR Audio CODEC interrupt 12 KMI0_INTR Keyboard/Mouse interrupt 13 KMI1_INTR Keyboard/Mouse interrupt 14 CLCDINTR Dis
Hardware Description 2.7 DMA signals The motherboard does not contain a DMA Controller (DMAC). However, it does enable routing of two DMA ACK/REQ handshake signal pairs from selected IO FPGA peripherals to CoreTile Express or LogicTile Express daughterboards. These daughterboards might contain a DMAC. See your daughterboard documentation or application note for more information. There are eight DMA handshake signal pairs that run between the daughterboard tile sites through the System Bus.
Hardware Description 2.8 JTAG and test connectors The motherboard is not equipped with an ARM debug JTAG connector. To debug the application code, connect a debugger to the JTAG connector on the CoreTile Express daughterboard. Note For convenience, you can connect the JTAG connector on the CoreTile Express daughterboard to the JTAG connector on the back panel. • • ARM DUI 0447J ID052914 Caution The Motherboard Express µATX contains several connectors used for manufacturing test.
Chapter 3 Configuration This chapter describes the configuration sequence for the Motherboard Express µATX and any attached daughterboards. It contains the following section: • Configuration environment on page 3-2. ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM. All rights reserved.
Configuration 3.1 Configuration environment This section describes the configuration environment and hardware of the Versatile Express system using the Motherboard Express μATX and CoreTile Express and LogicTile Express daughterboards. Figure 3-1 shows the configuration architecture.
Configuration • Power-on detect on the Motherboard Express, V2M-P1. • Configuration EEPROM on the CoreTile Express daughterboard and on the LogicTile Express daughterboard. • HDRY headers on the Motherboard Express, V2M-P1, CoreTile Express and LogicTile Express daughterboards.
Chapter 4 Programmers Model This chapter describes the memory map and the configuration registers for the peripherals on the motherboard. It contains the following sections: • About this programmers model on page 4-2 • Memory maps on page 4-3 • Register summary on page 4-8 • Register descriptions on page 4-10 • IO Peripherals and interfaces on page 4-26. ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM. All rights reserved.
Programmers Model 4.1 About this programmers model The following information applies to the Motherboard Express µATX registers: ARM DUI 0447J ID052914 • The base address is not fixed, and can be different for any particular system implementation. The offset of each register from the base address is fixed. • Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in Unpredictable behavior.
Programmers Model 4.2 Memory maps The memory map details depend on whether the daughterboard uses the ARM Legacy memory map or the ARM Cortex-A Series memory map. 4.2.1 ARM Legacy memory map Figure 4-1 shows an example of the Legacy system memory map when the motherboard is used with the CoreTile Express A9x4 daughterboard.
Programmers Model Table 4-1 shows the peripherals and memory on the motherboard using the ARM legacy memory map. The addresses are offsets from the base addresses of the SMB chip selects.
Programmers Model Table 4-1 Motherboard peripheral ARM legacy memory map (continued) 4.2.2 Peripheral Interface logic SMB chip select Address offset Reserved - CS3 0x00800000-0x01FFFFFF Ethernet SMSC LAN9118 CS3 0x02000000-0x02FFFFFF USB Philips ISP1761 CS3 0x03000000-0x03FFFFFF ARM Cortex-A Series memory map Figure 4-2 shows an example of the ARM Cortex-A Series memory map when the motherboard is used with the CoreTile Express A5x2 daughterboard.
Programmers Model Table 4-2 shows the peripherals and memory on the motherboard when using the ARM Cortex-A Series memory map. The addresses are offsets are from the base addresses of the SMB chip selects.
Programmers Model Table 4-2 Motherboard peripheral ARM Cortex-A Series memory map (continued) • • ARM DUI 0447J ID052914 Peripheral Interface logic SMB chip select Address offset Reserved - CS3 0x00150000-0x0015FFFF Serial Bus DVI Custom CS3 0x00160000-0x0016FFFF RTC ARM PL031 CS3 0x00170000-0x0017FFFF Reserved - CS3 0x00180000-0x0018FFFF Reserved - CS3 0x00190000-0x0019FFFF Compact Flash Custom CS3 0x001A0000-0x001AFFFF UART4 ARM PL011 CS3 0x001B0000-0x001BFFFF Reserved
Programmers Model 4.3 Register summary This section describes the system registers on the motherboard. Note All registers are 32 bits wide and do not support byte writes. Write operations must be word-wide and bits marked as reserved must be preserved using read-modify-write.
Programmers Model Table 4-3 Register map for status and system registers (continued) Offset Value Register Type Reset Description 0x0058 SYS_CFGSW RO/RWa 0x000000XXb Bits [7:0] are the soft configuration switches. See Config Switch Register on page 4-15. 0x005C SYS_24MHZ RO 0xXXXXXXXXb 32-bit counter clocked at 24MHz. See 24MHz Counter Register on page 4-16. 0x0060 SYS_MISC RO/RWa 0xXX0X0000b Miscellaneous control flags. See Miscellaneous Flags Register on page 4-16.
Programmers Model 4.4 Register descriptions This section describes Motherboard Express µATX registers. Table 4-3 on page 4-8 provides cross references to individual registers. 4.4.1 ID Register The SYS_ID Register characteristics are: Purpose Identifies the board and FPGA. Usage constraints See Table 4-4. Configurations See Table 4-4. Attributes See Table 4-3 on page 4-8. Figure 4-3 shows the bit assignments.
Programmers Model Configurations See Table 4-5. Attributes See Table 4-3 on page 4-8. Figure 4-4 shows the bit assignments. 31 30 29 28 27 8 7 Undefined 0 Soft user switch SW[1] SW[0] nUART0CTS nUART0DSR Figure 4-4 SYS_SW Register bit assignments Table 4-5 shows the bit assignments. Table 4-5 SYS_SW Register bit assignments 4.4.3 Bits Access Name Reset Description 31 Read-only SW[1] Indicates the value of physical configuration switch SW[1].
Programmers Model Figure 4-5 shows the bit assignments. 31 8 7 Undefined 0 LED[7:0] Figure 4-5 SYS_LED Register bit assignments Table 4-6 shows the bit assignments. Table 4-6 SYS_LED Register bit assignments 4.4.4 Bits Access Name Reset Description [31:8] Read-only - - Reserved [7:0] Read-write LED[7:0] 0xXX Set the corresponding register bit to 1 to light the LED. 100Hz Counter Register The SYS_100HZ Register characteristics are: Purpose A 32-bit counter incremented at 100Hz.
Programmers Model Table 4-8 shows the Flag registers.
Programmers Model 31 2 1 0 Undefined WPROT CARDIN Figure 4-6 SYS_MCI Register bit assignments Table 4-9 shows the bit assignments. Table 4-9 SYS_MCI Register bit assignments Bits Name Reset Description [31:2] - 0x0000000 Undefined, write ignored, read as zero. [1] WPROT bx Status of the Write Protect switch from the MCI connector, WPROT. [0] CARDIN bx Card detect: b0 b1 4.4.7 No card detected. Card detected.
Programmers Model Table 4-10 shows the bit assignments. Table 4-10 SYS_FLASH Register bit assignments Bits Name Reset Description [31:1] - 0x0000000 Undefined, write ignored, read as zero [0] FLASHWPn b0 b0 Enables the Lock-Down mechanism. The Lock-Down Block command puts the NOR Flash memory blocks into read-only state. The blocks cannot be reprogrammed, erased or unlocked. Overrides the Lock-Down mechanism. The Unlock Block command can unlock previously locked down NOR Flash memory blocks.
Programmers Model 4.4.9 24MHz Counter Register The SYS_24MHz Register characteristics are: Purpose Provides a 32-bit count value. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes See Table 4-3 on page 4-8. Table 4-12 shows the bit assignments. Table 4-12 SYS_24MHz Register bit assignments Bits Name Reset Description [31:0] SYS_24MHz The register is set to zero by a CB_nRST reset then continues to count.
Programmers Model Table 4-13 shows the bit assignments. Table 4-13 SYS_MISC Register bit assignment Bits Access Name Reset Description [31:28] Write ignored, read as zero - b0000 Undefined. [27] Read-write SB_EVENTI bX Event input from daughterboards. See your daughterboard documentation for more information specific to your board. [26:25] Read-write USBnOEN[1:0] bXX Setting these bits LOW enables control of ISP1761 DC/HC_SUSPEND signals from USB_SUSPEND[1:0].
Programmers Model Figure 4-3 on page 4-10 shows the bit assignments. 31 2 1 0 Undefined DMA select Figure 4-10 SYS_DMA Register bit assignments Table 4-14 shows the bit assignments. Table 4-14 SYS_DMA Register bit assignments 4.4.
Programmers Model Table 4-15 shows the bit assignments. Table 4-15 SYS_PROCID0 Register bit assignments Bits Name Reset Description [31:24] PROC_ID0 Depends on daughterboard Returns the ARM core or cluster type: 0x00 ARM7TDMI. 0x02 ARM9xx. 0x04 ARM1136. 0x06 ARM11MPCore. 0x08 ARM1156. 0x0A ARM1176. 0x0C Cortex-A9. 0x0E Cortex-A8. 0x10 Cortex-R4. 0x12 Cortex-A5. 0x14 Cortex-A15. 0x18 Cortex-A7. 0x16 Cortex-R5. 0x1A Cortex-R7. 0xFF CoreTile not supported.
Programmers Model Usage constraints See Table 4-16. Configurations See Table 4-16. Attributes See Table 4-3 on page 4-8. Figure 4-3 on page 4-10 shows the bit assignments. 31 24 23 PROC_ID1 20 19 BOARD REVISION 16 15 BOARD VARIANT 12 11 Undefined 0 HBI number Figure 4-12 SYS-PRODCID1 Register bit assignments Table 4-16 shows the bit assignments.
Programmers Model 4.4.14 System Configuration registers The following System configuration registers, SYS_CF, exist: • SYS_CFGDATA. • SYS_CFGCTRL. • SYS_CFGSTAT. The registers are collectively referred to as SYS_CFG registers. The registers enable communication between the MCC and Daughterboard Configuration Controller to read and write a variety of system parameters, for example: • Oscillators. • Voltage. • Current. • Power.
Programmers Model Note The same interface is accessible from the MCC command line. See the ARM® Versatile™ Express Configuration Technical Reference Manual CFG command. Configuration Control Register The SYS_CFGCTRL Register characteristics are: Purpose Controls the transfer of data across the SPI interface between the MCC and a Daughterboard Configuration Controller. Usage constraints See Table 4-18 and Table 4-19 on page 4-23. Configurations Available in all configurations.
Programmers Model Table 4-18 SYS_CFGCTRL Register bit assignments (continued) Bits Name Description [17:16] Site Describes the board site location of the device written to: b00 Motherboard. b01 Daughterboard 1. b10 Daughterboard 2. b11 Not used. [15:12] Position Describes the board stack position: 4-bit number for the position of the daughterboard in the stack 0-15 on a particular site. 0 represents the bottom of the stack. Set to 0 for the motherboard.
Programmers Model Configuration Status Register The SYS_CFGSTAT Register characteristics are: Purpose Describes if the transfer between the MCC and a Daughterboard Configuration Controller completes, or if there is an error during the transfer. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes See Table 4-3 on page 4-8. Figure 4-14 shows the register bit assignments.
Programmers Model else // set control register SYS_CFGCTRL = SYS_CFG_START | dcc | function | site | position | device // wait for complete flag to be set while (!(SYS_CFGSTAT & SYS_CFG_COMPLETE)) // check error status flag and return error flag if set if (SYS_CFGSTAT & SYS_CFG_ERROR) return FAILURE else // read data data = SYS_CFGDATA return SUCCESS ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM. All rights reserved.
Programmers Model 4.
Programmers Model 31 8 7 6 5 3 2 0 Undefined Reserved FIFO depth Number of channels Figure 4-15 AACI ID Register bit assignments Table 4-22 shows the register bit assignments. Table 4-22 Modified AACI PeriphID3 Register bit assignments Bit Access Name Description [31:8] Write as zeros, read is undefined - Undefined [7:6] Read-modify-write to preserve value Reserved Reserved [5:3] Read-only FIFO depth FIFO depth in compact mode: b000 4. b001 16. b010 32. b011 64. b100 128.
Programmers Model Table 4-23 provides information for the CLCDC. Table 4-23 CLCDC implementation Property Value Location Motherboard IO FPGA Memory base address • • ARM Legacy memory map: — SMB CS7 base address + 0x1F000. ARM Cortex-A Series memory map: — SMB CS3 base address + Ox1F0000. Interrupt 14 DMA - Release version ARM CLCDC PL111, version r0p2. Reference documentation ARM® PrimeCell Color LCD Controller (PL111) Technical Reference Manual.
Programmers Model The motherboard has been tested at 800 x 600 x 16-bit with a static color chart. However, practical resolution and color depth depend on available bus bandwidth. If a CLCDC in a daughterboard is the video source, the actual resolution range depends on the daughterboard CLCDC. 4.5.3 Compact Flash interface The Compact Flash interface is a custom AMBA AHB-compliant SoC peripheral that is developed, tested, and licensed by ARM.
Programmers Model 20 19 31 Undefined 16 15 Pulse 10 9 8 7 Undefined 3 2 1 0 Reserved CF_nCD2 CF_nCD1 CF_PWR_CONTROL CF_RESETn CFPOWER Figure 4-16 CF_CTRL Register bit assignments Table 4-25 shows the register bit assignments. Table 4-25 CF_CTRL Register bit assignments Bits Access Name Reset Description [31:20] Write ignored, read as zero - 0x00000 Undefined. [19:16] Read-write Pulse 0x00000 Pulse width. [15:10] Write ignored, read as zero - 0x00000 Undefined.
Programmers Model Table 4-26 provides information about the Ethernet interface. Table 4-26 Ethernet implementation Property Value Location Motherboard IO FPGA. Memory base address • • ARM Legacy memory map: — SMB CS3 base address + 0x2000000. ARM Cortex-A Series memory map: — SMB CS2 base address + Ox2000000. Interrupt 15. DMA None. Use memory to memory DMA to access the FIFO buffers in the LAN9118 Host Bus Interface. Release version Custom interface to external controller.
Programmers Model 4.5.5 Keyboard and Mouse Interface, KMI The PL050 PrimeCell PS2 Keyboard/Mouse Interface (KMI) is an AMBA-compliant SoC peripheral that is developed, tested, and licensed by ARM. Two KMIs are present on the motherboard: KMI0 Used for keyboard input. KMI1 Used for mouse input. The internal registers of the KMI interface are memory-mapped onto a static memory bus chip select.
Programmers Model • Cortex-A Series memory map: — The registers map onto the CS3 chip select. Note See the Technical Reference Manual for your daughterboard. Table 4-28 provides information about the MCI interface. Table 4-28 MCI implementation Property Value Location Motherboard IOFPGA Memory base address • • 4.5.
Programmers Model Table 4-29 provides information about the RTC. Table 4-29 RTC implementation Property Value Location Motherboard IO FPGA Memory base address • • ARM Legacy memory map: — SMB CS7 base address + 0x17000 Cortex-A Series: — SMB CS3 base address + 0x17000 Interrupt 4 DMA - Release version ARM RTC PL031 r1p0 Reference documentation ARM® PrimeCell Real Time Clock (PL031) Technical Reference Manual Note The motherboard Time-of-Year (TOY) clock updates the RTC on power-up.
Programmers Model Table 4-30 provides information about the serial bus interface. Table 4-30 Serial bus implementation Property Value Location Motherboard IO FPGA Memory base address • ARM Legacy memory map: — SMB CS7 base address + 0x2000 - PCIe. — SMB CS7 base address + 0x16000 - DVI. Cortex-A Series memory map: — SMB CS3 base address + 0x30000 - PCIe. — SMB CS3 base address + 0x16000 - DVI.
Programmers Model Table 4-33 show the registers that control the serial bus interface.
Programmers Model Table 4-34 provides information on the timers.
Programmers Model Table 4-35 provides information about the UART interfaces. Table 4-35 UART implementation Property Value Location Motherboard IO FPGA Memory base address • • ARM Legacy memory map: UART 0 SMB CS7 base address + 0x9000 UART 1 SMB CS7 base address + 0xA000 UART 2 SMB CS7 base address + 0xB000 UART 3 SMB CS7 base address + 0xC000.
Programmers Model Enabling UARTs You must set the variables MBLOG and DBLOG in the config.txt file to FALSE to enable you to use the UARTs. Example 4-2 shows the lines in the config.txt file that you must edit to enable the UARTs. Example 4-2 Example code in config.txt file to enable UARTs MBLOG: FALSE DBLOG: FALSE ;LOG MB MICRO TO UART1 in run mode ;LOG DB MICRO TO UART2/3 in run mode See the ARM® Versatile™ Express Configuration Technical Reference Manual for information on how to edit the config.
Programmers Model The ISP1761 has the following features: • Includes high-performance USB peripheral controller with integrated Serial Interface Engine, FIFO memory, and transceiver. • Configurable number of downstream and upstream hosts or functions. • USB host supports 480Mb/s, 12Mb/s, and 1.5Mb/s. • Programmable interrupts and DMA. • FIFO and 63KB on-chip RAM for USB. Table 4-37 shows the ISP1761 register address offsets from the CS3 base address.
Programmers Model • Cortex-A Series memory map: — The registers map onto the CS3 chip select. Note See the Technical Reference Manual for your daughterboard. Table 4-38 provides information about the Watchdog. Table 4-38 Watchdog implementation Property Value Location Motherboard IO FPGA Memory base address • • ARM Legacy memory map: — SMB CS7 base address + 0xF000 ARM Cortex-A Series memory map: — SMB CS2 base address + 0xF0000 Interrupt 0 DMA - Release version ARM WDOG SP805 r2p0.
Appendix A Signal Descriptions This appendix provides a summary of signals present on the motherboard connectors. It contains the following sections: • Audio CODEC interface on page A-2 • UART interface on page A-3. Note This appendix only covers non-standard connectors or non-standard signal connections to an industry-standard connector. ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM. All rights reserved.
Signal Descriptions A.1 Audio CODEC interface The motherboard provides three stacked 3.5mm jack connectors on the rear panel that enable you to connect to the analog microphone and auxiliary line level input and output on the CODEC. If no jack plug is inserted, the tip and sleeve of both the Mic In and Line In jack sockets are connected to analog ground to help prevent noise pickup. Figure A-1 shows the pinouts of the sockets.
Signal Descriptions A.2 UART interface The motherboard provides four serial transceivers on the rear panel of the enclosure. Figure A-2 shows the pin numbering for the 9-pin D-type male connector used on the V2M-P1 and Table A-1 shows the signal assignment for the connectors. Figure A-2 shows the pinout that is configured as a Data Communications Equipment (DCE) device.
Appendix B Specifications This appendix contains the specification for the motherboard. It contains the following sections: • Timing specifications on page B-2 • Electrical Specification on page B-7. ARM DUI 0447J ID052914 Copyright © 2009-2014, ARM. All rights reserved.
Specifications B.1 Timing specifications This section provides the timing specifications for the SMB bus. These timing specifications are required if you implement an SMB interface in a LogicTile Express daughterboard. All CoreTile Express daughterboards correctly implement the timing requirements in this section. B.1.1 SMB synchronous read Figure B-1 shows the synchronous read timing.
Specifications B.1.2 SMB synchronous write Figure B-2 shows the synchronous write timing. SMB_CLKO SMB_CLKI Tsmbis SMB_ADDR ADDR SMB_nADV Trc SMB_nCS Twp SMB_nWE Tsmbfih SMB_DATA RDATA Tperiod Tsmbov SMB_nWAIT Wait_req_SMB_CLKI Wait_req_SMB_CLKO Figure B-2 Synchronous write timing The intervals are: • Tsmbis = 6ns. • Tsmbov = 7.5ns. • Tsmbih = 0ns. • Twp = 2 cycles, minimum. • Trc_ncs7 = 5 cycles, minimum. • Trc_ncs3 = 7 cycles, minimum. All signals are clocked off SMB_CLKO.
Specifications B.1.3 SMB asynchronous read Figure B-3 shows the asynchronous read timing. SMB_CLKO Tsmbis SMB_ADDR ADDR Trc SMB_nCS Tsmbis SMB_nOE Tsmbov SMB_DATA Tsmboh RDATA SMB_nCSreg_in Tsmbov SMBF_nCS Tsmbov SMBF_nOE Tsmbfis SMBF_DATA RDATA SMBF_DATAreg_in RDATA SMB_DATAinternal RDATA Figure B-3 Asynchronous read timing The intervals are as follows: • Tsmbis = 6ns • Tsmbov = 7.
Specifications SMB_CLKO Tsmbis SMB_ADDR ADDR Trc SMB_nCS Tsmbis SMB_nWE SMB_DATA WDATA SMB_nCSreg_in Tsmbov SMBF_nCS Tsmbov Tsmbov SMBF_nWE SMBF_DATA SMBF_DATAreg_in WDATA SMBF_DATA WDATA Tsmbov Figure B-4 Asynchronous write timing The intervals are as follows: • Tsmbis = 6ns • Tsmbov = 7.5ns • Tsmbfis = 6ns • Tsmbfov = 6ns • Tsmboh = Tperiod/2 All SMB input signals are registered on the rising edge of SMB_CLKO. They are then registered a second time before being output on the IOFPGA SMB bus.
Specifications Site 1 Site 2 CB SMB1 to Site 1 Motherboard Configuration Controller SB_GCLK SMB2 to Site 2 Site 1 Site 2 MMB1 to Site 1 Interrupts and DMA control MMB2 to Site 2 Matrix, multiplexers, and bridges NOR FLASH 0 CS0 NOR FLASH 1 CS4 User SRAM CS1 Ethernet CS2 USB CS2 Video SRAM CS2 MMB MMB Mux DVI AACI Peripherals Compact Flash 2 x KMI SD/MMC CS3 4 x UART User LEDS PCIe I2C I/O FPGA Figure B-5 Video multiplexer FPGA timing The timing intervals are as follows: ARM DU
Specifications B.2 Electrical Specification This section provides information about the voltage and current characteristics for the motherboard. B.2.1 Power supply loading Table B-1 shows the current loading for the ATX power supply by the motherboard. Table B-1 Motherboard electrical characteristics Symbol Description Min Max Peak Unit 12V 12V from ATX power supply 0 10 10 A 5V 5V from ATX power supply 0 10 10 A 3.3V 3.
Appendix C Revisions This appendix describes the technical changes between released issues of this book. Table C-1 Issue A Change Location Affects No changes, first release - - Table C-2 Differences between Issue A and Issue B ARM DUI 0447J ID052914 Change Location Affects Remove USB and LAN from the Note about nCS3. Static Memory Bus on page 2-4. All versions. Clarified the location of the SB_GLCK signal. Figure 2-4 on page 2-13. All versions.
Revisions Table C-3 Differences between Issue B and Issue C Change Location Affects Switch names changed from: • Power on/off and reset push button to ON/OFF/Soft Reset push button • Standby push button to Hardware RESET push button See Figure 1-2 on page 1-4 and throughout the document. All versions. Title changed for ease of understanding to Power-on, on/off, and reset signals and section updated. Power up, on/off and reset signals on page 2-6. All versions.
Revisions Table C-4 Differences between Issue C and Issue D Change Location Affects Reference to ARM PrimeCell Multimedia Card Interface (Pl180) Technical Reference Manual added. ARM publications on page ix. All versions. SB_IRQ[] Interrupt signals table updated to reflect MultiMedia card interrupts in interrupts 9 and 10. Table 2-2 on page 2-18. All versions. The four methods to configure the motherboard OSC clocks are described beneath the Motherboard clocks table.
Revisions Table C-5 Differences between Issue D and Issue E ARM DUI 0447J ID052914 Change Location Affects Programmers Model updated to reflect the latest template. Chapter 4 Programmers Model. All versions. Text references, diagrams, and new diagrams added to include the new memory map, the ARM Cortex-A Series memory map. Existing references to existing memory map changed to ARM legacy memory map.
Revisions Table C-5 Differences between Issue D and Issue E (continued) Change Location Affects Example USBMSD directory structure updated to include images.txt in SITE1 directory. svf file updated to be isps_1v.svf. Section text updated to include references to images.txt file. Configuration files on page 3-14. Figure 3-6 on page 3-15. All versions. IMAGES section removed from example config.txt file to become example images.txt file in section on contents of directory for CoreTile Express boards.
Revisions Table C-6 Differences between Issue E and Issue F (continued) Change Location Affects Configuration chapter shortened. Information is now in a new document the ARM® Versatile™ Express Configuration Technical Reference Manual. Chapter 3 Configuration All versions. Changes cross-references to configuration and reset information inside this document to references to new document ARM® Versatile™ Express Configuration Technical Reference Manual.
Revisions Table C-9 Differences between Issue H and Issue I Change Location Affects Added Address Valid (nADV) signal to SMB timing diagrams. Figure B-1 on page B-2 Figure B-2 on page B-3 All versions Clarified maximum current loading of motherboard voltage regulators by CoreTile Express or LogicTile Express daughterboards.
