Specifications

OSCIN
/NR
/1 to /64
INTCLK
PLL
/NF
/1 to /256
VCOCLK
/OD
/1 to /8
post_ODCLK
/R
/1 to /32
PLLCLK
f = (f / NR) * NF / (OD * R)
PLLCLK OSCIN
f = (f / NR2) * NF2 / (OD2 * R2)
PLL2CLK OSCIN
PLL2CLK
/R2
/1 to /32
post_ODCLK2
/OD2
/1 to /8
VCOCLK2
INTCLK2
OSCIN
/NR2
/1 to /64
PLL#2
/NF2
/1 to /256
www.ti.com Standard Initialization Sequence for Hercules Microcontrollers
2.1 Initialize Stack Pointers for the CPU Supervisor (SVC) Operating Mode
Define the base addresses for the stacks used for the different operating modes. The addresses listed
below are only examples and can be defined by the application as required.
user: .word 0x08001000
svc: .word 0x08002000
Supervisor mode is a protected mode for the operating system and is entered upon taking a Supervisor
Call (SVC). This is also the default mode of the CPU after a CPU reset. It is important to initialize the
stack pointer for this mode before making any function call.
cps #0x13 ; switch to Supervisor mode if you are not already in this mode
ldr sp, svc
2.2 Configure PLLs
The Hercules microcontrollers contain a frequency-modulated phase-locked loop (FMPLL) macro that
allows the input oscillator frequency to be multiplied to a higher frequency than can be conveniently
achieved with an external resonator or crystal. Additionally, the FMPLL allows the flexibility to generate
many different frequency options from a fixed crystal or resonator.
The FMPLL allows the application to superimpose a “modulation frequency” signal on the selected base
frequency signal output from the FMPLL. This reduces the electromagnetic energy of the output signal by
spreading it across a controlled frequency range around the base frequency. This mode is disabled by
default, and the application can enable it in applications sensitive to noise emissions.
The Hercules microcontrollers also contain a second non-modulating PLL macro. This PLL#2 can be
independently configured to generate a second high-frequency clock source for specific uses, e.g.,
FlexRay communication clock source of 80 MHz.
2.2.1 FMPLL Block Diagram
Figure 3 shows a high-level block diagram of the FMPLL macro.
Figure 3. FMPLL Block Diagram
The parameters f
OSCIN
, f
post_ODCLK
and f
HCLK
are data sheet specifications. To identify the min/max limits on
these frequencies, see the device-specific data sheet.
5
SPNA106– September 2011 Initialization of Hercules™ ARM
®
Cortex™-R4F Microcontrollers
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