Specifications

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Standard Initialization Sequence for Hercules Microcontrollers

The interrupt enable set register 1 (REQENASET1) is shown in Figure 29.

Figure 29. Interrupt Enable Set Register 1 (REQENASET1) Address = 0xFFFFFE34

31 16

REQENASET[63:48]

R/WP-0

15 0

REQENASET[47:32]

R/WP-0

LEGEND: R = Read in all modes; WP = Write in priviledged mode; -n = value after reset

Setting any bit in these registers enables the corresponding interrupt request to trigger either an IRQ or an

FIR exception to the Cortex-R4F CPU.

The interrupt requests 0 and 1 are always enabled and cannot be disabled.

Similarly, there are registers to disable all 128 interrupts, except for interrupt requests 0 and 1. The

registers for disabling interrupt requests 0 to 63 are shown as follows.

The interrupt enable clear register 0 (REQENACLR0) is shown in Figure 30.

Figure 30. Interrupt Enable Clear Register 0 (REQENACLR0) Address = 0xFFFFFE40

31 16

REQENACLR[31:16]

R/WP:0

15 2 1 0

REQENACLR[15:0] Reserved

R/WP:0

LEGEND: R = Read in all modes; WP = Write in priviledged mode; -n = value after reset

The interrupt enable clear register 1 (REQENACLR1) is shown in Figure 31.

Figure 31. Interrupt Enable Clear Register 1 (REQENACLR1), Address = 0xFFFFFE44

31 16

REQENACLR[63:48]

R/WP-0

15 0

REQENACLR[47:32]

R/WP-0

LEGEND: R = Read in all modes; WP = Write in priviledged mode; -n = value after reset

Setting any bit in the interrupt enable clear registers disables the corresponding interrupt. When an

interrupt is disabled, it does not prevent the interrupt flag to get set when the interrupt condition is

generated but no IRQ or FIR exception is generated for the Cortex-R4F CPU.

2.22 Enable the Cortex-R4F CPU’s Vectored Interrupt Controller (VIC) Port

The CPU has a dedicated port that enables the Vectored Interrupt Manager (VIM) module to supply the

address of an interrupt service routine along with the interrupt (IRQ) signal. This provides faster entry into

the interrupt service routine versus the CPU having to decode the pending interrupts and identify the

highest priority interrupt to be serviced first.

SPNA106– September 2011 Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers

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