Specifications

ManualsBrandsARM ManualsComputer HardwareCortex R4F

www.ti.com

Standard Initialization Sequence for Hercules Microcontrollers

2.14 Enable Response to ECC Errors in Flash Module and TCRAM Module

The flash module has a Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) at

address 0xFFF87008. This register controls the ECC functionality implemented inside the flash module,

including support for the SECDED logic inside the Cortex-R4F CPU. The bits 3–0 of this register make up

the EDACEN field. EDACEN is configured to 0x5 by default. The application must configure EDACEN to

0xA in order to enable the flash module's support for the CPU's SECDED logic.

unsigned int temp;

temp = flashWREG->FEDACCTRL1;

temp = temp & 0xFFFFFFF0;

temp = temp | 0xA;

flashWREG->FEDACCTRL1 = temp;

The TCRAM interface module also includes support for the CPU's SECDED logic. This functionality is

enabled by default. For information on disabling / enabling this functionality, please refer to the TCRAM

Module chapter of the part's technical reference manual.

2.15 Enable the Cortex-R4F CPU’s Event Signaling Mechanism

The Cortex-R4F CPU has a dedicated event bus that is used to indicate that an event had occurred. This

event signaling is disabled upon reset and must be enabled. The Flash module and the RAM module

interfaces capture the ECC error events signaled by the CPU. This allows the application to further debug

the exact address, which caused the ECC error.

The CPU event signaling can be enabled by clearing the “X” bit of the performance monitoring unit’s

“Performance monitor control register, c9”. This can be done as shown below.

MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states

ORR r1, r1, #0x00000010

MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register

MRC p15,#0,r1,c9,c12,#0

2.16 Enable the Cortex-R4F CPU’s ECC Checking for ATCM and BTCM Interfaces

The CPU has internal ECC logic that protects all CPU accesses to the ATCM (Flash) and BTCM (RAM)

interfaces. This logic is not used by default and must be enabled by setting the B1TCMPCEN,

B0TCMPCEN and ATCMPCEN bits of the System control coprocessor’s Auxiliary control register, c1. This

can be done as shown below.

MRC p15, #0, r1, c1, c0, #1

ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMs

DMB

MCR p15, #0, r1, c1, c0, #1

2.17 Run Self-Test on the eFuse Controller SECDED Logic

Electrically programmable fuses (eFuses) are used to configure the part after de-assertion of power-on

reset (nPORRST). The eFuse values are read and loaded into internal registers as part of the

power-on-reset sequence. This is called the eFuse autoload. The eFuse values are protected with

single-bit error-correction, double-bit error-detection (SECDED) codes. These fuses are programmed

during the initial factory test of the device. The eFuse controller is designed so that the state of the eFuses

cannot be changed once the device is packaged.

For safety critical systems, it is important for the application to check the status of the eFuse controller

after a device reset. For more details on eFuse controller errors and the application sequence to check for

these errors, see the eFuse Controller chapter of the specific part's technical reference manual.

SPNA106– September 2011 Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers

Submit Documentation Feedback