Specifications

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25 VIM Interrupt Address Memory Map .................................................................................... 27
26 FIQ/IRQ Control Register 0 (FIRQPR0) Address = 0xFFFFFE10 .................................................. 30
27 FIQ/IRQ Control Register 1 (FIRQPR1) Address = 0xFFFFFE14 .................................................. 30
28 Interrupt Enable Set Register 0 (REQENASET0) Address = 0xFFFFFE30 ....................................... 30
29 Interrupt Enable Set Register 1 (REQENASET1) Address = 0xFFFFFE34 ....................................... 31
30 Interrupt Enable Clear Register 0 (REQENACLR0) Address = 0xFFFFFE40..................................... 31
31 Interrupt Enable Clear Register 1 (REQENACLR1), Address = 0xFFFFFE44.................................... 31
List of Tables
1 PLL Control Register (PLLCTL1) Field Descriptions ................................................................... 6
2 PLL Control Register 2 (PLLCTL2) Field Descriptions................................................................. 7
3 Clock Sources on Hercules Microcontrollers ............................................................................ 8
4 Flash Read Control Register (FRDCNTL) Field Descriptions ....................................................... 14
5 Flash State Machine Write Enable Control Register (FSM_WR_ENA) Field Descriptions...................... 15
6 Flash EEPROM Configuration Register (EEPROM_CONFIG) Field Descriptions................................ 15
7 Flash Bank Access Control Register (FBAC) Field Descriptions ................................................... 17
8 Flash Pump Access Control Register 1 (FPAC1) Field Descriptions............................................... 18
9 Flash Pump Access Control Register 2 (FPAC2) Field Descriptions............................................... 18
10 Clock Domains on Hercules Microcontrollers.......................................................................... 19
11 GCLK, HCLK , VCLKx Source Register (GHVSRC) Field Descriptions ........................................... 19
12 Asynchronous Clock Source Register (VCLKASRC) Field Descriptions........................................... 20
13 Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions....................... 24
14 Memory Self-Test / Initialization Control Register (MSIENA) Field Descriptions.................................. 25
2
Initialization of Hercules™ ARM
®
Cortex™-R4F Microcontrollers SPNA106– September 2011
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