Specifications

www.ti.com Standard Initialization Sequence for Hercules Microcontrollers
When the return stack detects a taken return instruction, the PFU issues an instruction fetch from the
location at the top of the return stack, and pops the return stack. The instructions that the PFU recognizes
as procedure returns are, in both the ARM and Thumb instruction sets:
→ LDMIA Rn{!}, {..,pc}
→ POP {..,pc}
→ LDMIB Rn{!}, {..,pc}
→ LDMDA Rn{!}, {..,pc}
→ LDMDB Rn{!}, {..,pc}
→ LDR pc, [sp], #4
→ BX Rm
2.7 Reset Handler
Each application has different levels of tolerance for different reset conditions. A typical reset handler is
presented below, which identifies all the causes of a reset condition on the Hercules MCUs.
/* read the system exception status register */
temp = systemREG1->SYSESR;
/* check for power-on reset condition */
if (temp & 0x8000)
{
/* clear all reset status flags */
systemREG1->SYSESR = 0xFFFF;
/* continue with normal start-up sequence */
}
else if (temp & 0x4000)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
}
else if (temp & 0x2000)
{
/* Reset caused due to windowed watchdog violation.
Add user code here to handle watchdog violation */
}
else if (temp & 0x20)
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register.
Add user code to handle CPU reset:
check for selftest completion without any error and continue start-up. */
}
else if (temp & 0x10)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
}
13
SPNA106– September 2011 Initialization of Hercules™ ARM
®
Cortex™-R4F Microcontrollers
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