Specifications

www.ti.com Standard Initialization Sequence for Hercules Microcontrollers
2.5 Enabling Floating-Point Coprocessor (FPU)
The floating-point coprocessor is disabled upon a CPU reset and must be enabled if the application
requires floating-point calculations. If a floating-point instruction is executed with the FPU disabled, an
undefined instruction exception is generated.
.def _coreEnableVfp_
.asmfunc
_coreEnableVfp_
; First enable access to the FPU
mrc p15, #0x00, r0, c1, c0, #0x02
orr r0, r0, #0xF00000
mcr p15, #0x00, r0, c1, c0, #0x02
; Now enable the FPU
mov r0, #0x40000000
fmxr fpexc, r0
bx lr
.endasmfunc
2.6 Initialization of Cortex-R4F Registers
The Hercules series of microcontrollers include dual Cortex-R4F CPUs running in a lock-step operation
mode. A Core Compare Module (CCM-R4) compares the output signals from each R4F CPU. Any
difference in the two CPUs’ outputs is flagged as a fault of a high-severity level. The CPU internal
registers are not guaranteed to power up in the same state for both the CPUs. The CPU pushes the
internal registers on to the stack on a function call, which could lead to the detection of a core compare
error. Therefore, the CPU internal core registers need to be initialized to a predefined state before any
function call is made.
.def _coreInitRegisters_
.asmfunc
_coreInitRegisters_
; After reset, the CPU is in the Supervisor mode (M = 0b10011)
mov r0, lr
mov r1, #0x0000
mov r2, #0x0000
mov r3, #0x0000
mov r4, #0x0000
mov r5, #0x0000
mov r6, #0x0000
mov r7, #0x0000
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
; Switch to FIQ mode (M = 0b10001)
cps #0x11
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
11
SPNA106– September 2011 Initialization of Hercules™ ARM
®
Cortex™-R4F Microcontrollers
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