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Application Report

SPNA106– September 2011

Initialization of Hercules™ ARM

Cortex™-R4F

Microcontrollers

Sunil Oak........................................................................................................................................

ABSTRACT

This application report provides a brief overview and initialization procedure of the TMS570LS31x series

and the RM4x series of microcontrollers in the Hercules family. "Hercules MCU" will be used henceforth in

this document to refer to any part in these series of microcontrollers.

The document also shows code fragments from source files that are generated using the nowGen tool. All

code constructs used in this document are defined in header files also generated by the same utility.

Contents

1 Block Diagram ............................................................................................................... 3

2 Standard Initialization Sequence for Hercules Microcontrollers ...................................................... 4

3 References ................................................................................................................. 32

List of Figures

1 Device Block Diagram...................................................................................................... 3

2 Color Legend for Block Diagram.......................................................................................... 3

3 FMPLL Block Diagram ..................................................................................................... 5

4 PLL Control Register 1 (PLLCTL1) Address = 0xFFFFFF70 ......................................................... 6

5 PLL Control Register 2 (PLLCTL2) Address = 0xFFFFFF74 ......................................................... 7

6 Clock Source Disable Register (CSDIS) Address = 0xFFFFFF30 ................................................... 8

7 Clock Source Disable Set Register (CSDISSET) Address = 0xFFFFFF34 ......................................... 9

8 Clock Source Disable Clear Register (CSDISCLR) Address = 0xFFFFFF38....................................... 9

9 Flash Read Control Register (FRDCNTL) Address = 0xFFF87000 ................................................ 14

10 Flash State Machine Write Enable Control Register (FSM_WR_ENA) Address = 0xFFF87288 ............... 15

11 Flash EEPROM Configuration Register (EEPROM_CONFIG) Address = 0xFFF872B8 ........................ 15

12 Flash Bank Fall-Back Control Register (FBFALLBACK) Address = 0xFFF87040................................ 16

13 Flash Bank Access Control Register (FBAC) Address = 0xFFF8703C ............................................ 17

14 Flash Pump Access Control Register 1 (FPAC1) Address = 0xFFF87048........................................ 18

15 Flash Pump Access Control Register 2 (FPAC2) Address = 0xFFF8704C ....................................... 18

16 GCLK, HCLK , VCLKx Source Register (GHVSRC) Address = 0xFFFFFF48 .................................... 19

17 Asynchronous Clock Source Register (VCLKASRC) Address = 0xFFFFFF4C................................... 20

18 Asynchronous Clock Configuration Register 1 (VCLKACON1) Address = 0xFFFFE140........................ 20

19 RTI Clock Source Register (RCLKSRC) Address = 0xFFFFFF50.................................................. 21

20 Peripheral Clock Control Register (CLKCNTL) Address = 0xFFFFFFD0.......................................... 21

21 Clock Control Register 2 (CLK2CNTL) Address = 0xFFFFE13C ................................................... 22

22 Memory Hardware Initialization Global Control Register (MINITGCR) Address = 0xFFFFFF5C............... 24

23 Memory Self-Test / Initialization Control Register (MSIENA) Address = 0xFFFFFF60 .......................... 25

24 Memory Self-Test / Initialization Status Register (MSTCGSTAT) Address = 0xFFFFFF68 ..................... 25

Hercules is a trademark of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM is a registered trademark of ARM Limited.

All other trademarks are the property of their respective owners.

SPNA106– September 2011 Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers

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Summary of content (33 pages)

PAGE 1
Application Report SPNA106 – September 2011 Initialization of Hercules™ ARM® Cortex™-R4F Microcontrollers Sunil Oak ........................................................................................................................................ ABSTRACT This application report provides a brief overview and initialization procedure of the TMS570LS31x series and the RM4x series of microcontrollers in the Hercules family.
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www.ti.com 25 VIM Interrupt Address Memory Map .................................................................................... 27 26 FIQ/IRQ Control Register 0 (FIRQPR0) Address = 0xFFFFFE10 .................................................. 30 27 FIQ/IRQ Control Register 1 (FIRQPR1) Address = 0xFFFFFE14 .................................................. 30 28 Interrupt Enable Set Register 0 (REQENASET0) Address = 0xFFFFFE30 .......................................
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Block Diagram www.ti.com 1 Block Diagram Section 1 shows a high-level block diagram of the superset TMS570LS31x microcontroller. For the actual block diagram relevant for any derivative of the TMS570LS series or for the RM4x series of microcontrollers, see the device-specific data sheet.
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Standard Initialization Sequence for Hercules Microcontrollers 2 www.ti.com Standard Initialization Sequence for Hercules Microcontrollers A basic sequence for initialization and configuration of the key features on a Hercules MCU is summarized below and detailed in the following sections. Some parts of the initialization sequence are not mandatory. Applications that are non-safety-critical can choose to not use the ECC feature for Flash and RAM accesses, for example.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.1 Initialize Stack Pointers for the CPU Supervisor (SVC) Operating Mode Define the base addresses for the stacks used for the different operating modes. The addresses listed below are only examples and can be defined by the application as required. user: svc: .word 0x08001000 .word 0x08002000 Supervisor mode is a protected mode for the operating system and is entered upon taking a Supervisor Call (SVC).
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com NOTE: The FMPLL takes (127 + 1024*NR) oscillator cycles to acquire lock to the target frequency, hence it is recommended to configure the FMPLL(s) and enable them as soon as possible in the device initialization. 2.2.2 FMPLL Slip Detector The FMPLL macro has a slip detector circuit that compares the OSCIN to the VCOCLK and flags any single-cycle slips.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com Table 1. PLL Control Register (PLLCTL1) Field Descriptions (continued) Bit Field 15-0 Value Description PLLMUL Defines the NF multiplier NF = (PLLMUL / 256) + 1 fVCOCLK = fINTCLK * NF The PLL control register 2 (PLLCTL2) is shown in Figure 5 and described in Table 2. Figure 5.
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Standard Initialization Sequence for Hercules Microcontrollers 2.3 www.ti.com Enable Clock Sources 2.3.1 Available Clock Sources on Hercules Microcontrollers The Hercules microcontrollers support seven different clock sources, as listed in Table 3. Table 3. Clock Sources on Hercules Microcontrollers Clock Source Number Clock Source Name Description OSCIN This is the primary oscillator, typically driven by an external resonator or crystal.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The clock source disable register (CSDISSET) is shown in Figure 7. Figure 7.
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Standard Initialization Sequence for Hercules Microcontrollers 2.4 www.ti.com Configure Oscillator Monitor The HF LPO clock source is used as a reference clock for monitoring the main oscillator. A failure is detected if the oscillator frequency falls outside the range: {fHFLPO / 4, fHFLPO*4}. The HF LPO frequency varies significantly over process corners as well as with changes in the core supply (VCC) and temperature.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.5 Enabling Floating-Point Coprocessor (FPU) The floating-point coprocessor is disabled upon a CPU reset and must be enabled if the application requires floating-point calculations. If a floating-point instruction is executed with the FPU disabled, an undefined instruction exception is generated. .def _coreEnableVfp_ .
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Standard Initialization Sequence for Hercules Microcontrollers mov mov r11, r12, www.ti.com #0x0000 #0x0000 ; Switch back to Supervisor Mode (M = 0b10011) cps #0x13 ; Initialize Floating Point Unit registers if FPU is used .
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com When the return stack detects a taken return instruction, the PFU issues an instruction fetch from the location at the top of the return stack, and pops the return stack. The instructions that the PFU recognizes as procedure returns are, in both the ARM and Thumb instruction sets: → → → → → → → 2.7 LDMIA Rn{!}, {..,pc} POP {..,pc} LDMIB Rn{!}, {..,pc} LDMDA Rn{!}, {..,pc} LDMDB Rn{!}, {..
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Standard Initialization Sequence for Hercules Microcontrollers 2.8 www.ti.com Configure Flash Access The Flash memory on the Hercules series microcontrollers is a non-volatile electrically erasable and programmable memory. The Hercules microcontrollers contain a digital module that manages all accesses to the Flash memory. A Flash access can be completed without any wait states required for bus master clock speeds up to 45 MHz.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com Figure 10. Flash State Machine Write Enable Control Register (FSM_WR_ENA) Address = 0xFFF87288 31 16 Reserved R-0 15 12 11 8 7 5 4 3 2 1 0 WR ENA Reserved R-0 R/WP010 LEGEND: R = Read; WP = Write in priviledge mode; -n = value after reset Table 5.
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Standard Initialization Sequence for Hercules Microcontrollers 2.9 www.ti.com Configure Flash Bank and Pump Power Modes The Flash banks and pump used on the Hercules series microcontrollers support three different operating modes to optimize power consumption.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com Each of the BANKPWRx fields configures the fall-back mode for a single Flash bank. The Hercules microcontrollers support up to 4 Flash banks.
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Standard Initialization Sequence for Hercules Microcontrollers flashWREG->FMAC = 0x00000000; flashWREG->FBAC |= 0x0000FF00; www.ti.com // Select flash bank0 // Select 255 * 16 HCLK cycles as the bank0 AGP The Flash pump access control register 1 (FPAC1) is shown in Figure 14 and described in Table 8. Figure 14.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com flashWREG->FPAC2 = 0x000000FF; // PSLEEP = 255 * 16 HCLK cycles 2.10 Clock Domains There are multiple clock domains on the Hercules microcontrollers to ease the configuration and controllability of the different modules using these clock domains (see Table 10). Table 10. Clock Domains on Hercules Microcontrollers 2.10.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com Table 11. GCLK, HCLK , VCLKx Source Register (GHVSRC) Field Descriptions (continued) Bit Field Value 23-20 Reserved 19-16 HVLPM 15-1 Reserved 0 GHVSRC Description 0 Reserved Defines the clock source used for the HCLK and VCLKx domains when the CPU clock domain GCLK is disabled. 0 Reserved Defines the clock source to be currently used for the GCLK, HCLK and VCLKx domains.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The asynchronous clock source register (VCLKASRC) is shown in Figure 19. Figure 19. RTI Clock Source Register (RCLKSRC) Address = 0xFFFFFF50 31 16 Reserved R-0 15 12 11 8 7 4 3 0 Reserved RTIDIV[1:0] Reserved RTI1SRC[3:0] R-0 R/WP-01 R-0 R/WP-1001 LEGEND: R = Read in all modes; WP = Write in priviledged mode; -n = value after reset • • 2.10.2 RTI1SRC field defines the clock source used for the RTI1CLK domain.
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Standard Initialization Sequence for Hercules Microcontrollers systemREG1->CLKCNTL |= 0x00000000U temp = systemREG1->CLKCNTL; systemREG1->CLKCNTL |= 0x00010000U; | (0U); 2.10.4 ; www.ti.com // VCLK2 = HCLK/1 // dummy read to cause delay // VCLK = HCLK/2 // Use FMPLL as source for RTI1CLK Configuring VCLK3 Frequency The VCLK3 clock signal is divided down from the HCLK clock signal. This divider is in the clock control register 2 (CLK2CNTL), which is shown in Figure 21. Figure 21.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.14 Enable Response to ECC Errors in Flash Module and TCRAM Module The flash module has a Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) at address 0xFFF87008. This register controls the ECC functionality implemented inside the flash module, including support for the SECDED logic inside the Cortex-R4F CPU. The bits 3–0 of this register make up the EDACEN field. EDACEN is configured to 0x5 by default.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.18 Run Self-Test on the Flash Module SECDED Logic The Flash module reads the “reset configuration vector” from address 0xF0080140 in the TI OTP region of Flash bank 0. This is a 64-bit value which is used to configure the device power domains, etc. The Flash module has built-in SECDED logic to correct any single-bit error in this vector or detect and flag and double-bit error in this vector.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com Figure 23. Memory Self-Test / Initialization Control Register (MSIENA) Address = 0xFFFFFF60 31 16 MSIENA[31:16] R/WP-0 15 0 MSIENA[15:0] R/WP-0 LEGEND: R = Read in all modes; WP = Write in priviledged mode; -n = value after reset Table 14.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The Cortex-R4F CPU can operate in one of several modes: • User mode (USR) is the usual mode for the execution of ARM or Thumb programs. It is used for executing most application programs. Many control registers on the Hercules microcontroller are not writable in user mode. cps ldr • irq #23 sp, abort #27 sp, undef System mode (SYS) is a privileged mode for the operating system.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The VIM module contains a memory that holds the starting addresses of the interrupt service routines for each interrupt enabled in the application. This memory starts at base address 0xFFF82000 on the Hercules microcontrollers. It is organized in 97 words of 32 bits. The VIM address memory map is shown below.
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Standard Initialization Sequence for Hercules Microcontrollers 2.21.1 www.ti.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.
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Standard Initialization Sequence for Hercules Microcontrollers 2.21.2 www.ti.com Configure Interrupts to be Fast Interrupts or Normal Interrupts Two registers in the VIM module allow each of the interrupts to be assigned to either the fast interrupt (FIQ) queue, or the normal interrupt queue (IRQ). The FIQ/IRQ control register 0 (FIRQPR0) is shown in Figure 26. Figure 26.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The interrupt enable set register 1 (REQENASET1) is shown in Figure 29. Figure 29.
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References www.ti.com The VIC port is disabled upon any CPU reset and must be enabled by the application. The VIC is enabled by setting the VE bit in the CPU’s System Control Register, as shown below. mrc orr mcr p15, #0, r0, c1, c0, r0, r0, #0x01000000 p15, #0, r0, c1, c0, #0 #0 2.23 Enable Normal Interrupts in the Cortex-R4F CPU The normal interrupt (IRQ) is disabled inside the Cortex-R4F CPU by default and after a CPU reset.
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