Specifications

OSCIN
/NR
/1 to /64
INTCLK
PLL
/NF
/1 to /256
VCOCLK
/OD
/1 to /8
post_ODCLK
/R
/1 to /32
PLLCLK
f = (f / NR) * NF / (OD * R)
PLLCLK OSCIN
f = (f / NR2) * NF2 / (OD2 * R2)
PLL2CLK OSCIN
PLL2CLK
/R2
/1 to /32
post_ODCLK2
/OD2
/1 to /8
VCOCLK2
INTCLK2
OSCIN
/NR2
/1 to /64
PLL#2
/NF2
/1 to /256
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com
2.5 Enable the Cortex-R4F CPU’s ECC Checking for ATCM Interface
The CPU has internal ECC logic that protects all CPU accesses to the ATCM (Flash) interface. This logic
is not used by default and must be enabled by setting the ATCMPCEN bit of the System control
coprocessor’s Auxiliary control register, c1.
2.6 Handle the Cause of Reset
Each application has different levels of tolerance for different reset conditions.
2.7 Configure PLLs
The Hercules microcontrollers contain a frequency-modulated phase-locked loop (FMPLL) macro that
allows the input oscillator frequency to be multiplied to a higher frequency than can be conveniently
achieved with an external resonator or crystal. Additionally, the FMPLL allows the flexibility to generate
many different frequency options from a fixed crystal or resonator.
The FMPLL allows the application to superimpose a “modulation frequency” signal on the selected base
frequency signal output from the FMPLL. This reduces the electromagnetic energy of the output signal by
spreading it across a controlled frequency range around the base frequency. This mode is disabled by
default, and the application can enable it in applications sensitive to noise emissions.
The Hercules microcontrollers also contain a second non-modulating PLL macro. This PLL#2 can be
independently configured to generate a second high-frequency clock source for specific uses, e.g.,
FlexRay communication clock source of 80 MHz.
2.7.1 FMPLL Block Diagram
Figure 3 shows a high-level block diagram of the FMPLL macro.
Figure 3. FMPLL Block Diagram
The parameters f
OSCIN
, f
post_ODCLK
and f
HCLK
are data sheet specifications. To identify the min/max limits on
these frequencies, see the device-specific data sheet.
NOTE: The FMPLL takes (127 + 1024*NR) oscillator cycles to acquire lock to the target frequency,
hence it is recommended to configure the FMPLL(s) and enable them as soon as possible in
the device initialization.
2.7.2 FMPLL Configuration
PLL1 is configured using two control registers, PLL Control 1 Register (PLLCTL1) and PLL Control 2
Register (PLLCTL2), located within the System module on the Hercules microcontrollers.
6
Initialization of Hercules™ ARM
®
Cortex™-R4F Microcontrollers SPNA106D–May 2013
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