Specifications

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Standard Initialization Sequence for Hercules Microcontrollers

2.1 Enable Floating-Point Coprocessor (FPU)

The floating-point coprocessor is disabled upon a CPU reset and must be enabled if the application

requires floating-point calculations. If a floating-point instruction is executed with the FPU disabled, an

undefined instruction exception is generated.

2.2 Initialize Cortex-R4F Registers

The Hercules series of microcontrollers include dual Cortex-R4F CPUs running in a lock-step operation

mode. A core compare module (CCM-R4) compares the output signals from each R4F CPU. Any

difference in the two CPUs’ outputs is flagged as a fault of a high-severity level. The CPU internal

registers are not guaranteed to power up in the same state for both the CPUs. The CPU pushes the

internal registers on to the stack on a function call, which could lead to the detection of a core compare

error. Therefore, the CPU internal core registers need to be initialized to a predefined state before any

function call is made.

The CPU’s call-return stack consists of a 4-entry circular buffer. When the CPU pre-fetch unit (PFU)

detects a taken procedure call instruction, the PFU pushes the return address onto the call-return stack.

The instructions that the PFU recognizes as procedure calls are, in both the ARM and Thumb instruction

sets:

→ BL immediate

→ BLX immediate

→ BLX Rm

When the return stack detects a taken return instruction, the PFU issues an instruction fetch from the

location at the top of the return stack, and pops the return stack. The instructions that the PFU recognizes

as procedure returns are, in both the ARM and Thumb instruction sets:

→ LDMIA Rn{!}, {..,pc}

→ POP {..,pc}

→ LDMIB Rn{!}, {..,pc}

→ LDMDA Rn{!}, {..,pc}

→ LDMDB Rn{!}, {..,pc}

→ LDR pc, [sp], #4

→ BX Rm

2.3 Enable Response to ECC Errors in Flash Interface Module

The Flash module has a Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) at

address 0xFFF87008. This register controls the ECC functionality implemented inside the Flash module,

including support for the SECDED logic inside the Cortex-R4F CPU. The bits 3–0 of this register make up

the EDACEN field. EDACEN is configured to 0x5 by default. The application must configure EDACEN to

0xA in order to enable the flash module's support for the CPU's SECDED logic.

2.4 Enable the Cortex-R4F CPU’s Event Signaling Mechanism

The Cortex-R4F CPU has a dedicated event bus that is used to indicate that an event had occurred. This

event signaling is disabled upon reset and must be enabled. The Flash module and the RAM module

interfaces capture the ECC error events signaled by the CPU. This allows the application to further debug

the exact address, which caused the ECC error.

The CPU event signaling can be enabled by setting the “X” bit of the performance monitoring unit’s

“Performance monitor control register, c9”.

SPNA106D–May 2013 Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers

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