Specifications

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Standard Initialization Sequence for Hercules Microcontrollers

2.27 On-Chip SRAM Auto-Initialization

The system module on the Hercules microcontroller allows all on-chip SRAMs to be initialized in hardware.

This is especially essential since all the on-chip memories support some form of error detection. The CPU

data RAM supports ECC while the peripheral memories support parity error detection. The auto-

initialization mechanism also initializes the ECC or parity memories, as required.

2.28 Run a Self-Test on All Peripheral RAMs' Parity Protection Mechanism

Accesses to most peripheral RAMs on this microcontroller are protected by parity error detection. Each of

the peripherals with the parity error detection for its associated memory also includes a self-test mode to

ensure that it is indeed capable of detecting and reporting a parity error on an access to the peripheral

RAM. These self-test mechanisms can be used by the application before enabling use of the concerned

peripheral.

2.29 Enable the Cortex-R4F CPU’s Vectored Interrupt Controller (VIC) Port

The CPU has a dedicated port that enables the VIM module to supply the address of an interrupt service

routine along with the interrupt (IRQ) signal. This provides faster entry into the interrupt service routine

versus the CPU having to decode the pending interrupts and identify the highest priority interrupt to be

serviced first.

The VIC port is disabled upon any CPU reset and must be enabled by the application. The VIC is enabled

by setting the VE bit in the CPU’s System Control Register (SYS).

2.30 Vectored Interrupt Manager (VIM) Configuration

The VIM module on the Hercules microcontrollers supports flexible mapping of interrupt request channels

and the interrupt generating sources. The default mapping between the channel number and the

interrupting module is defined in the device-specific data sheet. The interrupt channel number also defines

the inherent priority between the channels, with the lower numbered channel having the higher priority.

That is, the priority decreases in the following order: channel 0 → channel 1 → channel 2 → … channel

95.

For this application report, assume that the application prefers to keep the default priority order between

the channels. For details on the control registers for changing the mapping between interrupt channels

and sources, see the device-specific technical reference manual.

The VIM module contains a memory that holds the starting addresses of the interrupt service routines for

each interrupt enabled in the application. This memory starts at base address 0xFFF82000 on the

Hercules microcontrollers. It is organized in 97 words of 32 bits. The VIM address memory map is shown

in Figure 4.

SPNA106D–May 2013 Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers

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