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Standard Initialization Sequence for Hercules Microcontrollers

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2.19 Run a Diagnostic Check on the Programmable Built-In Self-Test (PBIST) Controller

The PBIST engine is used to run memory test routines on all on-chip memories. It is critical for the

application to rely on this engine being able to detect and report a memory fault condition. Therefore it is

necessary for the application to test this error detection and reporting mechanism before actually using it

to test the on-chip memories. This is done by choosing to run a RAM test routine on a ROM memory. This

test must generate a memory test failure. The application can look for the error flag to ensure that the

PBIST controller can indeed detect and report a memory test failure. For information on how to configure

the PBIST controller for executing specific memory test algorithms on selected on-cip memories, see the

device-specific technical reference manual .

2.20 Start a Self-Test on the CPU RAM Using the PBIST Controller

The CPU RAM is tested first, so that the application can continue to execute while other memories are

being tested later. For information on configuring the PBIST controller, see the device-specific technical

reference manual.

2.21 Initialize the CPU RAM

The system module hardware for auto-initialization of on-chip memories also initializes the associated

ECC or parity locations. This mechanism is now used to initialize the CPU RAM. This process clears the

CPU RAM to all zeros and also programs the corresponding ECC locations.

2.22 Enable the Cortex-R4F CPU’s ECC Checking for BxTCM Interface

The CPU has internal ECC logic that protects all CPU accesses to the BTCM (RAM) interfaces. This logic

is not used by default and must be enabled by setting the B1TCMPCEN and B0TCMPCEN bits of the

System control coprocessor’s Auxiliary control register, c1.

2.23 Start a Self-Test on All Dual-Port Memories’ Using the PBIST Controller

Separate algorithms are used for testing single-port versus dual-port on-chip SRAMs. For information on

executing the self-test on the on-chip memories using the programmable BIST (PBIST) engine, see the

device-specific technical reference manual.

2.24 Run a Self-Test on CPU's ECC Logic for Accesses to TCRAM

The CPU TCRAM was initialized earlier, so that all TCRAM is cleared to zeros and the corresponding

correct ECC locations are programmed. The test of the CPU's ECC logic for accesses to TCRAM involves

corrupting the ECC locations to create single-bit and two-bit ECC errors. For the sequence to test the

CPU's ECC logic for accesses to TCRAM, see the device-specific technical reference manual or the

initialization example project. Note that reading from a TCRAM location with a double-bit ECC error

causes the CPU to take a data abort exception. The initialization example project also includes an

example data abort handler.

2.25 Run a Self-Test on CPU's ECC Logic for Accesses to Program Flash

The Flash interface module supports a diagnostic mode (mode 7) that allows the application to test the

CPU's ECC logic for accesses to program Flash. For the sequence to test the CPU's ECC logic for

accesses to program Flash, see the device-specific technical reference manual or the initialization

example project. Note that reading from a program Flash location with a double-bit ECC error causes the

CPU to take a data abort exception. The initialization example project also includes an example data abort

handler.

2.26 Start a Self-Test on All Single-Port Memories’ Using the PBIST Controller

The CPU RAM can be excluded from this testing as it has already been verified before. For information on

executing the self-test on the on-chip memories using the programmable BIST (PBIST) engine, see the

device-specific technical reference manual.

Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers SPNA106D–May 2013

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