Specifications

ManualsBrandsARM ManualsComputer HardwareCortex R4F

Application Report

SPNA106D–May 2013

Initialization of Hercules™ ARM

Cortex™-R4F

Microcontrollers

SunilOak

ABSTRACT

This application report provides a brief overview and initialization procedure of the TMS570LS31x series

and the RM4x series of microcontrollers in the Hercules family. "Hercules MCU" will be used henceforth in

this document to refer to any part in these series of microcontrollers.

The document also shows code fragments from source files that are generated using the HALCoGen tool.

All code constructs used in this document are defined in header files also generated by the same utility.

The HALCode Generator tool can be downloaded from the following URL: http://www.ti.com/tool/halcogen.

Contents

1 Block Diagram ............................................................................................................... 2

2 Standard Initialization Sequence for Hercules Microcontrollers ...................................................... 3

3 References ................................................................................................................. 15

List of Figures

1 Device Block Diagram...................................................................................................... 2

2 Color Legend for Block Diagram.......................................................................................... 2

3 FMPLL Block Diagram ..................................................................................................... 6

4 VIM Interrupt Address Memory Map .................................................................................... 14

List of Tables

1 Clock Sources on Hercules Microcontrollers ............................................................................ 7

2 Clock Domains on Hercules Microcontrollers.......................................................................... 10

Hercules is a trademark of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM is a registered trademark of ARM Limited.

All other trademarks are the property of their respective owners.

SPNA106D–May 2013 Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers

Submit Documentation Feedback

Summary of content (16 pages)

PAGE 1
Application Report SPNA106D – May 2013 Initialization of Hercules™ ARM® Cortex™-R4F Microcontrollers Sunil Oak ABSTRACT This application report provides a brief overview and initialization procedure of the TMS570LS31x series and the RM4x series of microcontrollers in the Hercules family. "Hercules MCU" will be used henceforth in this document to refer to any part in these series of microcontrollers. The document also shows code fragments from source files that are generated using the HALCoGen tool.
PAGE 2
Block Diagram 1 www.ti.com Block Diagram Section 1 shows a high-level block diagram of the superset TMS570LS31x microcontroller. For the actual block diagram relevant for any derivative of the TMS570LS series or for the RM4x series of microcontrollers, see the device-specific data sheet.
PAGE 3
www.ti.com 2 Standard Initialization Sequence for Hercules Microcontrollers Standard Initialization Sequence for Hercules Microcontrollers A basic sequence for initialization and configuration of the key features on a Hercules MCU is summarized below and many steps are detailed in the following sections. The source code example accompanying this application report demonstrates many of the suggested steps. Some parts of the initialization sequence are not mandatory.
PAGE 4
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 28. Start a self-test on all on-chip dual-port SRAMs using the PBIST controller (Section 2.23). 29. Run the self-test on the CPU's SECDED logic for accesses to main data RAM (B0TCM and B1TCM) (Section 2.24). 30. Run the self-test on the CPU's SECDED logic for accesses to the main Flash memory (ATCM) (Section 2.25). 31. Wait for self-test to complete and pass on all on-chip dual-port SRAMs. 32.
PAGE 5
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.1 Enable Floating-Point Coprocessor (FPU) The floating-point coprocessor is disabled upon a CPU reset and must be enabled if the application requires floating-point calculations. If a floating-point instruction is executed with the FPU disabled, an undefined instruction exception is generated. 2.
PAGE 6
Standard Initialization Sequence for Hercules Microcontrollers 2.5 www.ti.com Enable the Cortex-R4F CPU’s ECC Checking for ATCM Interface The CPU has internal ECC logic that protects all CPU accesses to the ATCM (Flash) interface. This logic is not used by default and must be enabled by setting the ATCMPCEN bit of the System control coprocessor’s Auxiliary control register, c1. 2.6 Handle the Cause of Reset Each application has different levels of tolerance for different reset conditions. 2.
PAGE 7
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com PLL2 is configured using a single PLL Control 3 Register (PLLCTL3) in the System module. 2.8 2.8.1 Enable Clock Sources Available Clock Sources on Hercules Microcontrollers The Hercules microcontrollers support seven different clock sources, as listed in Table 1. Table 1.
PAGE 8
Standard Initialization Sequence for Hercules Microcontrollers | 0x00000020U | 0x00000040U; www.ti.com // Enable clock source 5 // Enable clock source 6 The above configuration enables clock sources 0, 1, 4, 5, and 6. Of the clock sources that are enabled, number 0, 4 and 5 are enabled by default and will have become valid by the time the processor is released from reset upon a power-up. These are the main oscillator and the two outputs from the internal reference oscillator.
PAGE 9
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The Hercules MCUs also have a separate Flash bank (bank #7) that is dedicated for data storage. This bank can be used to emulate an EEPROM. Accesses to this Flash bank are configured via a separate EEPROM Emulation Configuration Register (EEPROM_CONFIG) in the Flash module. A write operation to the EEPROM_CONFIG register must first be enabled by configuring the Flash State Machine Write Enable Control Register (FSM_WR_ENA).
PAGE 10
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.14 Run Self-Test on the Flash Module SECDED Logic The Flash module reads the “reset configuration vector” from address 0xF0080140 in the TI OTP region of Flash bank 0. This is a 64-bit value that is used to configure the device power domains, etc. The Flash module has built-in SECDED logic to correct any single-bit error in this vector or detect and flag and double-bit error in this vector.
PAGE 11
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The clock sources for the VCLKA3 and VCLKA4 domains are selected via the Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1). The clock source for the RTI1CLK domain is selected via the RTI Clock Source Register (RCLKSRC). 2.15.2 Example Clock Domain Mapping systemREG1->GHVSRC = | | systemREG1->VCLKASRC = | systemREG1->RCLKSRC = | 2.15.
PAGE 12
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.19 Run a Diagnostic Check on the Programmable Built-In Self-Test (PBIST) Controller The PBIST engine is used to run memory test routines on all on-chip memories. It is critical for the application to rely on this engine being able to detect and report a memory fault condition. Therefore it is necessary for the application to test this error detection and reporting mechanism before actually using it to test the on-chip memories.
PAGE 13
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.27 On-Chip SRAM Auto-Initialization The system module on the Hercules microcontroller allows all on-chip SRAMs to be initialized in hardware. This is especially essential since all the on-chip memories support some form of error detection. The CPU data RAM supports ECC while the peripheral memories support parity error detection. The autoinitialization mechanism also initializes the ECC or parity memories, as required. 2.
PAGE 14
Standard Initialization Sequence for Hercules Microcontrollers www.ti.com Interrupt vector table address space 0xFFF82000 Phantom Vector 0xFFF82004 Channel 0 Vector 0xFFF82008 Channel 1 Vector 0xFFF82178 Channel 93 Vector 0xFFF8217C Channel 94 Vector Figure 4. VIM Interrupt Address Memory Map 2.30.
PAGE 15
References www.ti.com • • • Initialization of global and static variables defines in C/C++ Initialization of global constructors Make a function call to branch to the main application These requirements could be different for each compiler. The compiler reference manual must be referred to identify the specific requirements for the compiler being used. 2.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.