Specifications

www.ti.com Standard Initialization Sequence for Hercules Microcontrollers
2 Standard Initialization Sequence for Hercules Microcontrollers
A basic sequence for initialization and configuration of the key features on the TMS570LS043x,
TMS570LS033x, and RM42L432 microcontrollers is summarized below and many steps are detailed in the
following sections. The source code example accompanying this application report demonstrates many of
the suggested steps. Some parts of the initialization sequence are not mandatory. For example,
applications that are non-safety-critical can choose to not use the error correction coding (ECC) feature for
Flash and RAM accesses. Each application must also have its specific exception handling scheme: reset
handler, abort handler, and so forth. The code generated using the hardware abstraction layer code
generator (HALCoGen) includes template handling routines for each exception. These routines need to be
modified as required by the application.
1. Initialize the CPU registers, including stack pointers (Section 2.1).
2. Enable the Flash interface module's response to an ECC error indicated by the CPU on accesses to
Flash (Section 2.2).
3. Enable the CPU's Event Bus export mechanism (Section 2.3).
4. Enable the CPU's Single-Error-Correction Double-Error-Detection (SECDED) logic for accesses to
Flash memory (CPU's ATCM interface) (Section 2.4).
5. Handle the cause of reset to determine whether or not to continue with the start-up sequence
(Section 2.5)
6. Check if any ESM group3 error was indicated during power-up. If any ESM group3 error occurred
during the power-up, it is not safe to continue code execution and the microcontroller initialization
process can be stopped at this point. The subsequent steps in this sequence assume that there was
no ESM group3 error during power-up.
7. Configure phase-locked loop (PLL) control registers with the largest value for the last-stage of the
dividers (R-dividers) (Section 2.6).
8. Enable the PLLs (Section 2.7).
9. Run the eFuse controller start-up checks and start the self-test on the eFuse controller SECDED logic
(Section 2.8).
10. Release the peripherals from reset and enable clocks to all peripherals (Section 2.9).
11. Set up the device-level multiplexing options as well as the input/output (I/O) multiplexing.
12. Wait for the eFuse controller ECC logic self-test to complete and check the results.
13. Set up the Flash module for the required wait states and pipelined mode (Section 2.10).
14. Set up the Flash bank and pump power modes (Section 2.11).
15. Trim the LPO (Section 2.12).
16. Run the self-test on the SECDED logic embedded inside the Flash module (Section 2.13).
17. Wait for main PLL output to become valid.
18. Map the device clock domains to the desired clock sources (Section 2.14).
19. Reduce the values of the R-dividers in steps to attain the target PLL output frequency for both PLL1
and PLL2.
20. Run a diagnostic check on the CPU self-test controller (Section 2.15). A CPU reset is asserted upon
completion of the CPU self-test. Therefore, the initialization steps leading up to the reset handler will
be repeated.
21. Run the built-in self-test for the CPU (LBIST) (Section 2.16). A CPU reset is asserted upon completion
of the CPU self-test. Therefore, the initialization steps leading up to the reset handler will be repeated.
22. Run a diagnostic check on the CPU compare module (CCM-R4) (Section 2.17).
23. Run a diagnostic check on the memory self-test controller (Section 2.18).
24. Start a self-test on the CPU RAM using the programmable built-in self-test (PBIST) controller and wait
for this self-test to complete and pass (Section 2.19).
25. Initialize the CPU RAM using the system module hardware initialization mechanism so that the ECC
region for the CPU RAM is also initialized (Section 2.20).
26. Enable the CPU's SECDED logic for accesses to CPU RAM memory (CPU's B0TCM and B1TCM
interfaces) (Section 2.21).
3
SPNA163–September 2012 Initialization of the TMS570LS043x, TMS570LS033x and RM42L432
Hercules ARM Cortex-R4 Microcontrollers
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