Specifications

Standard Initialization Sequence for Hercules Microcontrollers www.ti.com
2.29.2 Enabling and Disabling Interrupts
Each interrupt request can be enabled or disabled using the Interrupt Enable Set (REQENASETx) and
Interrupt Enable Clear (REQENACLRx) registers. The interrupt requests 0 and 1 are always enabled and
cannot be disabled. When an interrupt is disabled, it does not prevent the interrupt flag from getting set
when the interrupt condition is generated but no IRQ or FIQ exception is generated for the Cortex-R4
CPU.
2.30 Enable Interrupts in the Cortex-R4 CPU
Interrupts (IRQ and FIQ) are disabled inside the Cortex-R4 CPU by default and after a CPU reset. The
normal interrupt can be enabled by clearing the "I" bit of the Current Program Status Register (CPSR)
inside the Cortex-R4 CPU, while the fast interrupt (FIQ) can be enabled by clearing the "F" bit of the
CPSR.
2.31 Setup the Error Signaling Module (ESM) Responses to Group1 Errors
The ESM allows the application to choose the module response to errors in the Group1 classification.
These are errors of the lowest severity and can be handled by the application by generating an interrupt to
the CPU. The ESM also offers the capability to indicate any group1 errors on the external nERROR pin.
2.32 Additional Initializations Required by Compiler
If the source program is written using C or C++, the TI compiler requires the creation of the C and C++
run-time environment. This includes:
• Initialization of copy table, if required
• Initialization of global and static variables defined in C and C++
• Initialization of global constructors
• Make a function call to branch to the main application
These requirements could be different for each compiler. The compiler reference manual must be referred
to identify the specific requirements for the compiler being used.
2.33 Other Initialization Steps Not Described in this Document
The following is an additional list of operations that an application can perform during the device
initialization.
• Verify that the DCC module can detect and report a frequency mismatch error.
• Configure the DCC module to continuously monitor the PLL output frequency.
• Several bus masters on the TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontroller
include their own memory protection units to protect against accesses to certain parts of the memory
map. It is recommended to ensure that violations of these MPU restrictions are detected and flagged
as ESM errors.
• Configure the MPU for each bus masters
• Run a check on the program Flash memory using CRC.
• Calibrate the embedded ADC module for any offset error.
• Run a self-test on all ADC inputs to ensure that they are not open or shorted to power or ground.
• Run an I/O loop-back check on all peripheral signals.
• Configure the windowed watchdog module service window size as well as the module response to a
window violation.
• Setup the RTI module to generate periodic interrupts as necessary.
• Configure desired access permissions for peripherals using the PCR registers.
• Configure any external safety companion chip, (for example, TI TPS6538x, for online diagnostic
operation).
14
Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 SPNA163–September 2012
Hercules ARM Cortex-R4 Microcontrollers
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