Specifications

Interrupt vector table address space

0xFFF82000

0xFFF82004

0xFFF82008

Phantom Vector

Channel 0 Vector

Channel 1 Vector

Channel 93 Vector

Channel 94 Vector

0xFFF82178

0xFFF8217C

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Standard Initialization Sequence for Hercules Microcontrollers

2.28 Enable the Cortex-R4 CPU’s Vectored Interrupt Controller (VIC) Port

The CPU has a dedicated port that enables the VIM module to supply the address of an interrupt service

routine along with the interrupt (IRQ) signal. This provides faster entry into the interrupt service routine

versus the CPU having to decode the pending interrupts and identify the highest priority interrupt to be

serviced first.

The VIC port is disabled upon any CPU reset and must be enabled by the application. The VIC is enabled

by setting the VE bit in the CPU’s System Control Register (SYS).

2.29 Vectored Interrupt Manager (VIM) Configuration

The VIM module on the TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers

supports flexible mapping of interrupt request channels and the interrupt generating sources. The default

mapping between the channel number and the interrupting module is defined in the device-specific data

sheet. The interrupt channel number also defines the inherent priority between the channels, with the

lower numbered channel having the higher priority. That is, the priority decreases in the following order:

channel 0 → channel 1 → channel 2 → … channel 95.

For this application report, assume that the application prefers to keep the default priority order between

the channels. For details on the control registers for changing the mapping between interrupt channels

and sources, see the device-specific technical reference manual.

The VIM module contains a memory that holds the starting addresses of the interrupt service routines for

each interrupt enabled in the application. This memory starts at base address 0xFFF82000 on the

TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers. It is organized in 96 words of

32 bits. The VIM address memory map is shown in Figure 3.

Figure 3. VIM Interrupt Address Memory Map

2.29.1 Configure Interrupts to be Fast Interrupts or Normal Interrupts

Each interrupt request to the VIM can be configured to be forwarded to the CPU as a fast interrupt request

(FIQ) or a normal interrupt request (IRQ). The FIQ and IRQ Program Control Registers (FIRQPRx) allow

this selection.

Interrupt requests 0 and 1 are always FIQ. All others are IRQ interrupts by default.

NOTE: An interrupt request mapped to FIQ cannot use the CPU’s VIC port.

SPNA163–September 2012 Initialization of the TMS570LS043x, TMS570LS033x and RM42L432

Hercules ARM Cortex-R4 Microcontrollers

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