Specifications

Standard Initialization Sequence for Hercules Microcontrollers

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2.20 Initialize the CPU RAM

The system module hardware for auto-initialization of on-chip memories also initializes the associated

ECC or parity locations. This mechanism is now used to initialize the CPU RAM. This process clears the

CPU RAM to all zeros and also programs the corresponding ECC locations.

2.21 Enable the Cortex-R4 CPU’s ECC Checking for BxTCM Interface

The CPU has internal ECC logic that protects all CPU accesses to the BTCM (RAM) interfaces. This logic

is not used by default and must be enabled by setting the B1TCMPCEN and B0TCMPCEN bits of the

System control coprocessor’s Auxiliary control register, c1.

2.22 Start a Self-Test on All Dual-Port Memories’ Using the PBIST Controller

Separate algorithms are used for testing single-port versus dual-port on-chip SRAMs. For information on

executing the self-test on the on-chip memories using the programmable BIST (PBIST) engine, see the

device-specific technical reference manual.

2.23 Run a Self-Test on CPU's ECC Logic for Accesses to TCRAM

The CPU TCRAM was initialized earlier, so that all TCRAM is cleared to zeros and the corresponding

correct ECC locations are programmed. The test of the CPU's ECC logic for accesses to TCRAM involves

corrupting the ECC locations to create single-bit and two-bit ECC errors. For the sequence to test the

CPU's ECC logic for accesses to TCRAM, see the device-specific technical reference manual or the

initialization example project. Note that reading from a TCRAM location with a double-bit ECC error

causes the CPU to take a data abort exception. The initialization example project also includes an

example data abort handler.

2.24 Run a Self-Test on CPU's ECC Logic for Accesses to Program Flash

The Flash interface module supports a diagnostic mode (mode 7) that allows the application to test the

CPU's ECC logic for accesses to program Flash. For the sequence to test the CPU's ECC logic for

accesses to program Flash, see the device-specific technical reference manual or the initialization

example project. Note that reading from a program Flash location with a double-bit ECC error causes the

CPU to take a data abort exception. The initialization example project also includes an example data abort

handler.

2.25 Start a Self-Test on All Single-Port Memories’ Using the PBIST Controller

The CPU RAM can be excluded from this testing as it has already been verified before. For information on

executing the self-test on the on-chip memories using the programmable BIST (PBIST) engine, see the

device-specific technical reference manual.

2.26 On-Chip SRAM Auto-Initialization

The system module on the Hercules microcontroller allows all on-chip SRAMs to be initialized in hardware.

This is especially essential since all the on-chip memories support some form of error detection. The CPU

data RAM supports ECC while the peripheral memories support parity error detection. The auto-

initialization mechanism also initializes the ECC or parity memories, as required.

2.27 Run a Self-Test on All Peripheral RAMs' Parity Protection Mechanism

Accesses to peripheral RAMs on this series of microcontroller are protected by parity error detection. Each

of the peripherals with the parity error detection for its associated memory also includes a self-test mode

to ensure that it is indeed capable of detecting and reporting a parity error on an access to the peripheral

RAM. These self-test mechanisms can be used by the application before enabling use of the concerned

peripheral.

Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 SPNA163–September 2012

Hercules ARM Cortex-R4 Microcontrollers

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