Specifications

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Standard Initialization Sequence for Hercules Microcontrollers

2.14.2 Example Clock Domain Mapping

systemREG1->GHVSRC = (0U << 24U) // Use main oscillator as wake up source for GHV CLK

| (0U << 16U); // Use main oscillator for HV CLK when GCLK is off

| (1U); // Use FMPLL as current source for GHV CLK

systemREG1->VCLKASRC = (0U); // Use main oscillator for DCANx bit timings

systemREG1->RCLKSRC = (1U << 8U) // Set the RTI1CLK divider to divide-by-2

| (0U); // Use FMPLL as source for RTI1CLK

2.14.3 Configuring VCLK , VCLK2 Frequencies

The VCLK and VCLK2 clock signals are divided down from the HCLK clock signal. These are independent

dividers that can be configured via the system module clock control register (CLKCNTL).

NOTE:

• VCLK2 frequency must also be an integer multiple of VCLK frequency.

• There must be some delay between configuring the divide ratios for VCLK2 and VCLK.

2.15 Run a Diagnostic Check on CPU Self-Test Controller (STC)

This involves running one CPU self-test interval in STC check mode. The STC self-check mode causes a

stuck-at-0 fault to be introduced inside one of the two CPUs for there to be an STC failure. If no STC

failure is indicated, this would mean that the STC is not capable of detecting a fault inside the CPU, and

device operation is not reliable. For information on the configuration and execution of the STC self-test,

see the device-specific technical reference manual. The CPU will be reset once the STC self-test is

completed. The reset handler routine can resume the device initialization from the next step in the

sequence.

2.16 Run CPU Self-Test (LBIST)

For information on the configuration and execution of the CPU self-test, see the device-specific technical

reference manual. The CPU will be reset once the self-test is completed. The reset handler routine can

resume the device initialization from the next step in the sequence.

2.17 Run a Diagnostic Check on the CPU Compare Module (CCM-R4)

The CCM-R4 compares the dual Cortex-R4 CPU outputs on each CPU clock cycle. Any mismatch is

indicated as an ESM group2 error. This ensures that the two CPUs are indeed operating in a lock-step

mode. The CCM-R4 module also allows the application to test the different error conditions using built-in

self-test routines. For information on how to configure the CCM-R4 in a self-test mode, see the device-

specific technical reference manual.

2.18 Run a Diagnostic Check on the Programmable Built-In Self-Test (PBIST) Controller

The PBIST engine is used to run memory test routines on all on-chip memories. It is critical for the

application to rely on this engine being able to detect and report a memory fault condition. Therefore, it is

necessary for the application to test this error detection and reporting mechanism before actually using it

to test the on-chip memories. This is done by choosing to run a RAM test routine on a ROM memory. This

test must generate a memory test failure. The application can look for the error flag to ensure that the

PBIST controller can indeed detect and report a memory test failure. For information on how to configure

the PBIST controller for executing specific memory test algorithms on selected on-chip memories, see the

device-specific technical reference manual .

2.19 Start a Self-Test on the CPU RAM Using the PBIST Controller

The CPU RAM is tested first, so that the application can continue to execute while other memories are

being tested later. For information on configuring the PBIST controller, see the device-specific technical

reference manual.

SPNA163–September 2012 Initialization of the TMS570LS043x, TMS570LS033x and RM42L432

Hercules ARM Cortex-R4 Microcontrollers

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