Specifications

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Standard Initialization Sequence for Hercules Microcontrollers

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There are dedicated locations within the TI OTP sector of Flash bank 0 that are programmed to have

single-bit and double-bit errors. Specifically, a 32-bit or 64-bit read from the address 0xF00803F0 results

in a single-bit error indication, and a 32-bit or 64-bit read from the address 0xF00803F8 results in a

double-bit error indication. These locations can be read by the application to ensure that the Flash

interface module is capable of detecting single-bit and double-bit errors upon reads from the OTP.

2.14 Clock Domains

All further initialization steps are now required to be performed at the max operating frequency for the

application. The application must now wait for the PLL to lock to its target frequency, and then map the

device clock domains to the desired clock sources. There are multiple clock domains on the

TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers to ease the configuration and

controllability of the different modules using these clock domains (see Table 2).

Table 2. Clock Domains on Hercules Microcontrollers

Domain Name Clock Name Comments

GCLK controls all the CPU sub-systems, including the floating point

CPU clock domain GCLK

unit (FPU), and the memory protection unit (MPU)

HCLK shares the same clock source as GCLK, and is always the

System bus clock domain HCLK

same frequency as HCLK.

VCLK_sys is used for the system modules such as VIM, ESM, SYS,

System peripheral clock domain VCLK_sys and so forth. VCLK_sys is divided down from HCLK by a

programmable divider from 1 to 16.

VCLK is the primary peripheral clock, and is synchronous with

VCLK_sys. VCLK2 is a secondary peripheral clock and is reserved

for use by the enhanced timer module (N2HET) and the associated

transfer unit (HTU). VCLK2 is also divided down from HCLK by a

programmable divider from 1 to 16. f

HCLK

must be an integer multiple

Peripheral clock domains VCLK, VCLK2

of f

VCLK2

, f

VCLK2

must be an integer multiple of f

VCLK

. NOTE: The clock

domain used for eQEP is VCLK; however, in order to provide an

extra level of control to the clocking of eQEP, VCLK clocking to

eQEP may be disabled separately from the VCLK domain

through CDDIS bit 9.

This clock domain is reserved for use by special communication

modules that have strict jitter constraints. For the TMS570LS043x,

TMS570LS033x, and RM42L432 series of microcontrollers this is

limited to the DCAN modules. The protocol for DCAN

Asynchronous clock domain VCLKA1

communication does not allow modulated clocks to be used for the

baud rate generation. The asynchronous clocks allow the clock

sources for the baud clocks to be decoupled from the GCLK, HCLK

and VCLKx clock domains.

This clock is used for generating the periodic interrupts by the RTI

Real-time Interrupt clock domains RTI1CLK

module.

2.14.1 Mapping Clock Domains to Clock Sources

The system module on the TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers

contains registers that allow the clock domains to be mapped to any of the available clock sources.

The clock source for the GCLK, HCLK , and VCLKx domains is selected by the GCLK, HCLK, VCLK, and

VCLK2 Source Register (GHVSRC).

The clock sources for the VCLKA1 domain is selected via the Peripheral Asynchronous Clock Source

The clock source for the RTI1CLK domain is selected via the RTI Clock Source Register (RCLKSRC).

Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 SPNA163–September 2012

Hercules ARM Cortex-R4 Microcontrollers

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