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Application Report

SPNA163–September 2012

Initialization of the TMS570LS043x, TMS570LS033x and

RM42L432 Hercules ARM Cortex-R4 Microcontrollers

Charles Davenport............................................................................................................................

ABSTRACT

This application report provides a brief overview and initialization procedure of the TMS570LS043x,

TMS570LS033x, and RM42L432 series of microcontrollers in the Hercules™ family. "Hercules MCU" will

be used henceforth in this document to refer to any part in these series of microcontrollers.

The document also shows code fragments from source files that are generated using the HALCoGen tool.

All code constructs used in this document are defined in header files also generated by the same utility.

Nearly all of the project collateral and source code discussed in this application report can be generated

using the HalCoGen tool v3.02.02 or higher.

Contents

1 Block Diagram ............................................................................................................... 2

2 Standard Initialization Sequence for Hercules Microcontrollers ...................................................... 3

3 Using HalCoGen to Generate the Code ................................................................................ 15

4 References ................................................................................................................. 15

List of Figures

1 Device Block Diagram...................................................................................................... 2

2 FMPLL Block Diagram ..................................................................................................... 6

3 VIM Interrupt Address Memory Map .................................................................................... 13

List of Tables

1 Clock Sources on Hercules Microcontrollers............................................................................ 6

2 Clock Domains on Hercules Microcontrollers.......................................................................... 10

Hercules is a trademark of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM is a registered trademark of ARM Limited.

All other trademarks are the property of their respective owners.

SPNA163–September 2012 Initialization of the TMS570LS043x, TMS570LS033x and RM42L432

Hercules ARM Cortex-R4 Microcontrollers

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Summary of content (16 pages)

PAGE 1
Application Report SPNA163 – September 2012 Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 Hercules ARM Cortex-R4 Microcontrollers Charles Davenport ............................................................................................................................ ABSTRACT This application report provides a brief overview and initialization procedure of the TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers in the Hercules™ family.
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Block Diagram 1 www.ti.com Block Diagram Section 1 shows a high-level block diagram of the superset TMS570LS043x and RM42L432 microcontrollers. For the actual block diagram relevant for any derivative of the TMS570LS series or for the RM4x series of microcontrollers, see the device-specific data sheet.
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www.ti.com 2 Standard Initialization Sequence for Hercules Microcontrollers Standard Initialization Sequence for Hercules Microcontrollers A basic sequence for initialization and configuration of the key features on the TMS570LS043x, TMS570LS033x, and RM42L432 microcontrollers is summarized below and many steps are detailed in the following sections. The source code example accompanying this application report demonstrates many of the suggested steps.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 27. Start a self-test on all on-chip dual-port SRAMs using the PBIST controller (Section 2.22). 28. Run the self-test on the CPU's SECDED logic for accesses to main data RAM (B0TCM and B1TCM) (Section 2.23). 29. Run the self-test on the CPU's SECDED logic for accesses to the main Flash memory (ATCM) (Section 2.24). 30. Wait for self-test to complete and pass on all on-chip dual-port SRAMs. 31.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com The CPU’s call-return stack consists of a 4-entry circular buffer. When the CPU pre-fetch unit (PFU) detects a taken procedure call instruction, the PFU pushes the return address onto the call-return stack.
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Standard Initialization Sequence for Hercules Microcontrollers 2.6 www.ti.com Configure PLLs The TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers contain a frequencymodulated phase-locked loop (FMPLL) macro that allows the input oscillator frequency to be multiplied to a higher frequency than can be conveniently achieved with an external resonator or crystal. Additionally, the FMPLL allows the flexibility to generate many different frequency options from a fixed crystal or resonator.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com Table 1. Clock Sources on Hercules Microcontrollers (continued) Clock Source Number 2.7.2 Clock Source Name Description 2 Not implemented No clock signal is connected to source 2. This clock source must not be enabled or chosen for any clock domain. 3 EXTCLKIN External clock input. This clock source must only be enabled if there is an actual external clock source connected to the identified device terminal for EXTCLKIN.
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Standard Initialization Sequence for Hercules Microcontrollers 2.8 www.ti.com Run Self-Test on the eFuse Controller SECDED Logic Electrically programmable fuses (eFuses) are used to configure the part after de-assertion of power-on reset (nPORRST). The eFuse values are read and loaded into internal registers as part of the power-onreset sequence. This is called the eFuse autoload. The eFuse values are protected with single-bit errorcorrection, double-bit error-detection (SECDED) codes.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.11 Configure Flash Bank and Pump Power Modes The Flash banks and pump used on the TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers support three different operating modes to optimize power consumption.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com There are dedicated locations within the TI OTP sector of Flash bank 0 that are programmed to have single-bit and double-bit errors. Specifically, a 32-bit or 64-bit read from the address 0xF00803F0 results in a single-bit error indication, and a 32-bit or 64-bit read from the address 0xF00803F8 results in a double-bit error indication.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.14.2 Example Clock Domain Mapping systemREG1->GHVSRC = | | systemREG1->VCLKASRC = systemREG1->RCLKSRC = | 2.14.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.20 Initialize the CPU RAM The system module hardware for auto-initialization of on-chip memories also initializes the associated ECC or parity locations. This mechanism is now used to initialize the CPU RAM. This process clears the CPU RAM to all zeros and also programs the corresponding ECC locations. 2.
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Standard Initialization Sequence for Hercules Microcontrollers www.ti.com 2.28 Enable the Cortex-R4 CPU’s Vectored Interrupt Controller (VIC) Port The CPU has a dedicated port that enables the VIM module to supply the address of an interrupt service routine along with the interrupt (IRQ) signal. This provides faster entry into the interrupt service routine versus the CPU having to decode the pending interrupts and identify the highest priority interrupt to be serviced first.
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Standard Initialization Sequence for Hercules Microcontrollers 2.29.2 www.ti.com Enabling and Disabling Interrupts Each interrupt request can be enabled or disabled using the Interrupt Enable Set (REQENASETx) and Interrupt Enable Clear (REQENACLRx) registers. The interrupt requests 0 and 1 are always enabled and cannot be disabled.
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Using HalCoGen to Generate the Code www.ti.com 2.34 Call the Main Application This is a normal function call when using C and C++. It could be a branch or branch-link to the name of the routine that executes the application. For example: main(); exit(); 3 Using HalCoGen to Generate the Code Although it is not the intent of this document to serve as a guide to using HalCoGen, below are the minimum steps necessary to generate the initialization code described in this document.
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