Datasheet

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C bus interface RM0352
96/138 DocID024647 Rev 1
10.2.18 I
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C peripheral identification register 0 (I2C_PERIPHID0)
Table 88. I
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C peripheral identification register 0 (I2C_PERIPHID0)
Address: I2CBaseAddress + 0xFE0
Type: R
Reset: 0x00000024
Description: The I2C_PERIPHID0-3 registers are four 8-bit registers, that span address
location 0xFE0 to 0xFEC. The registers are read-only.
10.2.19 I
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C peripheral identification register 1 (I2C_PERIPHID1)
Table 89. I
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C peripheral identification register 1 (I2C_PERIPHID1)
Address: I2CBaseAddress + 0xFE4
Type: R
Reset: 0x00000000
Description: I
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C peripheral identification register 1.
[7:1] DSA7: slave address in dual addressing mode.
[0] DUAL: dual addressing mode enable.
0: only SA7 is recognized in 7-bit addressing mode.
1: both SA7 and DSA7 are recognized in 7-bit addressing mode.
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C peripheral identification register 0 (I2C_PERIPHID0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PARTNUMBER0
RR
[7:0] PARTNUMBER0: these bits read back as 0x024.
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C peripheral identification register 1 (I2C_PERIPHID1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DESIGNER0 PARTNUMBER1
RRR
[7:4] DESIGNER0: these bits read back as 0x80.
[3:0] PARTNUMBER1: these bits read back as 0x024.