Datasheet

I
2
C bus interface RM0352
94/138 DocID024647 Rev 1
Note: The reset value is valid only when I
2
C frequency equal to 48 MHz. If frequency changes the
user must program the register and this value must be greater than 4.
To set the timing register we use Equation 3.
• Standard, fast-mode and fast-mode plus:
Equation 3
Thd-dat = N * Ti2c-clk + Pad_delay
with:
N: value to be programmed
Thd-dat: value required by I
2
C standard
Pad_delay: Pad delay
10.2.15 I
2
C hold time START condition F/S (I2C_THDSTA_FST_STD)
Table 85. I
2
C hold time START condition F/S (I2C_THDSTA_FST_STD)
Address: I2CBaseAddress + 0x050
Type: RW
Reset: 0x003F00E2
Description: The I2C_THDSTA_FST_STD register, that controls the hold time START
condition for F/S mode. The register is read-write.
[8:0] I2C_THDDAT: hold time data value
In master or slave mode, when the I
2
C controller detect a failing edge in SCL
line, the counter, which is loaded by the I2C_THDDAT, is launched. Once the
I2C_THDDAT value is reached, the data is transferred.
I
2
C hold time START condition F/S (I2C_THDSTA_FST_STD)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED I2C_THDSTA_FST RESERVED I2C_THDSTA_STD
RRW RRW
[24:16] I2C_THDSTA_FST: hold time START condition value for fast mode. When
the START condition is asserted, the decimeter loads the value of the
I2C_THDSTA_FST for fast mode, once the I2C_THDSTA_FST value is
reached the SCL line asserts low.
[8:0] I2C_THDSTA_STD: hold time START condition value for standard mode
When the START condition is asserted, the decimeter loads the value of
I2C_THDSTA_STD for standard mode, once the I2C_THDSTA_STD value is
reached the SCL line asserts low.