Datasheet

DocID024647 Rev 1 93/138
RM0352 I
2
C bus interface
137
Description: The I2CMISR register indicates the interrupt sources after masking. For the
description of each single bit, refer to the register I2C_RISR. The output signal
int_gbl is asserted when at least one interrupt source of this register is
pending.
10.2.13 I
2
C interrupt clear register (I2C_ICR)
Table 83. I
2
C interrupt clear register (I2C_ICR)
Address: I2CBaseAddress + 0x38
Type: RW
Reset: 0x00000000
Description: The I2C_ICR register indicates the interrupt sources after masking. For the
description of each single bit, refer to the register I2C_RISR. When writing to
this register, each data bit that is set to 1b causes the corresponding bit in the
status registers to be cleared. Data bits that are set to 0b have no effect on the
corresponding bit in the register.
10.2.14 I
2
C hold time data (I2C_THDDAT)
Table 84. I
2
C hold time data (I2C_THDDAT)
Address: I2CBaseAddress + 0x04C
Type: RW
Reset: 0x00000014
Description: The I2C_THDDAT register is an 8-bit registers, that controls the hold time data
for F/S mode. The register is read-write.
I
2
C interrupt clear register (I2C_ICR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
TIMEOUTIC
PECERRIC
MTDWSIC
RESERVED
BERRIC
MALIC
SALIC
RESERVED
STDIC
MTDIC
WTSRIC
RFSEIC
RFSRIC
LBRIC
RESERVED
TXFOVRIC
RESERVED
RWWW R WWR R WWWWWW W R
I
2
C hold time data (I2C_THDDAT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED I2C_THDDAT
RRW