Datasheet

I
2
C bus interface RM0352
90/138 DocID024647 Rev 1
1: master arbitration lost.
[23] SAL: slave arbitration lost (SMBUS mode). SAL is set when the slave loses
the arbitration during the data phase. A collision occurs when 2 devices
transmit simultaneously 2 opposite values on the serial dataline. The device
that is pulling up the line, identifies the collision reading a 0 value on the
sda_in signal, stops the transmission, releases the bus and waits for the idle
state (STOP condition received) on the bus line. The device which transmits
the first unique zero wins the bus arbitration. This interrupt is cleared setting
the related bit of the I2C_ICR register.
0: no slave arbitration lost.
1: slave arbitration lost.
[20] STD: slave transaction done. STD is set when a slave operation (write-to-
slave or read-from- slave) has been executed. The application shall read the
related transaction status (I2C_SR register), the pending data in the Rx FIFO
(only for a write-to-slave operation) and clear this interrupt (transaction
acknowledgment). A subsequent slave operation will be notified
(I2C_RISR:WTSR and I2C_RISR:RFSR interrupt bits assertion) after the
clearing of this interrupt, meanwhile the I
2
C clock line will be stretched low.
A subsequent master operation can be issued (writing the I2C_MCR register)
after the clearing of this interrupt. This interrupt is cleared setting the related
bit of the I2C_ICR register.
0: slave transaction acknowledged.
1: slave transaction done (ready for acknowledgment).
[19] MTD: master transaction done. MTD is set when a master operation (master
write or master read) has been executed after STOP condition. The
application shall read the related transaction status (I2C_SR register), the
pending data in the Rx FIFO (only for a master read operation) and clear this
interrupt (transaction acknowledgment). A subsequent master operation can
be issued (writing the I2C_MCR register) after the clearing of this interrupt.
A subsequent slave operation will be notified (I2C_RISR:WTSR and
I2C_RISR:RFSR interrupt bits assertion) after the clearing of this interrupt,
meanwhile the I
2
C clock line will be stretched low. This interrupt is cleared
setting the related bit of the I2C_ICR register.
0: master transaction acknowledged.
1: master transaction done (ready for acknowledgment).
[18] WTSR: write-to-slave request. WTSR is set when a write-to-slave operation
is received (I
2
C slave is addressed) from the I
2
C line. This interrupt is cleared
setting the related bit of the I2C_ICR register.
0: none write-to-slave request pending.
1: write-to-slave request is pending.
[17] RFSE: read-from-slave empty. RFSE is set when a read-from-slave operation
is in progress and the Tx FIFO is empty. On the assertion of this interrupt, the
CPU shall download in the Tx FIFO the data required for the slave operation.
This bit is self cleared writing in the Tx FIFO. At the end of the read-from-
slave operation this bit is cleared although the Tx FIFO is empty.