Datasheet

DocID024647 Rev 1 89/138
RM0352 I
2
C bus interface
137
• When set in slave mode: slave resets the communication and lines are
released by hardware.
• When set in master mode: STOP condition sent by hardware.
• Cleared by software writing in I2C_ICR, or by hardware when I2C_CR:
PE = 0.
[29] PECERR: PEC error in reception (SMBUS mode)
0: no PEC error: receiver returns ACK after PEC reception
(if I2C_CR:NACK = 0).
1: PEC error: receiver returns NACK after PEC reception (whatever I2C_CR:
NACK).
• Cleared by software writing in I2C_ICR, or by hardware when I2C_CR:
PE = 0.
[28] MTDWS: master transaction done without stop. MTDWS is set when
a master operation (write or read) has been executed and stop (I2C_MCR: P
field) is not programmed. The application shall read the related transaction
status (I2C_SR register), the pending data in the Rx FIFO (only for a master
read operation) and clear this interrupt (transaction acknowledgment).
A subsequent master operation can be issued (writing the I2C_MCR register)
after the clearing of this interrupt. A subsequent slave operation will be
notified (I2C_RISR: WTSR and I2C_RISR: RFSR interrupt bits assertion)
after the clearing of this interrupt, meanwhile the I
2
C clock line will be
stretched low. This interrupt is cleared setting the related bit of the I2C_ICR
register.
0: master transaction acknowledged
1: master transaction done (ready for acknowledgment) and stop is not
applied into the I
2
C bus.
[25] BERR: bus error. BERR is set when an unexpected START/STOP condition
occurs during a transaction. The related actions are different, depending on
the type of operation is in progress (TBD). The status code word in the
I2C_SR contains a specific error tag (CAUSE field) for this error condition.
This interrupt is cleared setting the related bit of the I2C_ICR register.
0: no bus error detection
1: bus error detection
[24] MAL: master arbitration lost. MAL is set when the master loses the arbitration
(only for debugging). The status code word in the I2C_SR contains a specific
error tag (CAUSE field) for this error condition. A collision occurs when 2
stations transmit simultaneously 2 opposite values on the serial line. The
station that is pulling up the line, identifies the collision reading a 0 value on
the sda_in signal, stops the transmission, leaves the bus and waits for the
idle state (STOP condition received) on the bus line before to retry the same
transaction. The station which transmits the first unique zero wins the bus
arbitration. This interrupt is cleared setting the related bit of the I2C_ICR
register.
0: no master arbitration lost.