Datasheet

I
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C bus interface RM0352
88/138 DocID024647 Rev 1
10.2.11 I
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C raw interrupt status register (I2C_RISR)
Table 81. I
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C raw interrupt status register (I2C_RISR)
Address: I2CBaseAddress + 0x30
Type: R
Reset: 0x00000013
[3] TXFOVRM: Tx FIFO overrun mask. TXFOVRM enables the interrupt bit
TFXOVR.
0: TXFOVR interrupt is disabled.
1: TXFOVR interrupt is enabled.
[2] TXFFM: Tx FIFO full mask. TXFFM enables the interrupt bit TXFF.
1: TXFF interrupt is enabled.
0: TXFF interrupt is disabled.
[1] TXFNEM: Tx FIFO nearly empty mask. TXFNEM enables the interrupt bit
TXFNE.
0: TXFNE interrupt is disabled.
1: TXFNE interrupt is enabled.
[0] TXFEM: Tx FIFO empty mask. TXFEM enables the interrupt bit TXFE.
0: TXFE interrupt is disabled.
1: TXFE interrupt is enabled.
I
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C raw interrupt status register (I2C_RISR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
TIMEOUT
PECERR
MTDWS
RESERVED
BERR
MAL
SAL
RESERVED
STD
MTD
WTSR
RFSE
RFSR
LBR
RESERVED
RXFF
RXFNF
RXFE
TXFOVR
TXFF
TXFNE
TXFE
RRRR R RRR R RRRRRR R RRRRRR R
Description: The I2C_RISR register indicates the interrupt sources prior to masking.
[30] TIMEOUT: timeout or Tlow error (SMBUS mode)
0: no timeout error
1: SCL remained LOW for 25 ms (timeout)
or
master cumulative clock low extend time more than 10 ms (Tlow:mext)
or