Datasheet

I
2
C bus interface RM0352
86/138 DocID024647 Rev 1
10.2.10 I
2
C interrupt mask set/clear register (I2C_IMSCR)
Table 80. I
2
C interrupt mask set/clear register (I2C_IMSCR)
Address: I2CBaseAddress + 0x2C
Type: R/W
Reset: 0x00000000
I
2
C interrupt mask set/clear register (I2C_IMSCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
TIMEOUTM
PECERRM
MTDWSM
RESERVED
BERRM
MALM
SALM
RESERVED
STDM
MTDM
WTSRM
RFSEM
RFSRM
LBRM
RESERVED
RXFFM
RXFNFM
RXFEM
TXFOVRM
TXFFM
TXFNEM
TXFEM
R
R/
W
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Description: I
2
C interrupt mask set/clear register
[30] TIMEOUTM: Timeout or Tlow error mask. TIMEOUTM enables the interrupt
bit.
TIMEOUT(SMBUS)
0: TIMEOUT interrupt is disabled, but checked internally.
1: TIMEOUT interrupt is enabled.
[29] PECERRM: PEC error in reception mask. PECERRM enables the interrupt
bit.
PECERR(SMBUS)
0: PECERR interrupt is disabled.
1: PECERR interrupt is enabled.
[28] MTDWSM: master transaction done without stop mask. MTDWSM enables
the interrupt bit.
MTDWS.
0: MTDWS interrupt is disabled.
1: MTDWS interrupt is enabled.
[25] BERRM: bus error mask. BERRM enables the interrupt bit BERR.
0: BERR interrupt is disabled.
1: BERR interrupt is enabled.
[24] MALM: master arbitration lost mask. MALM enables the interrupt bit MAL.
0: MAL interrupt is disabled.
1: MAL interrupt is enabled.