Datasheet

DocID024647 Rev 1 85/138
RM0352 I
2
C bus interface
137
10.2.9 I
2
C baud-rate counter register (I2C_BRCR)
Table 79. I
2
C baud-rate counter register (I2C_BRCR)
Address: I2CBaseAddress + 0x28
Type: R/W
Reset: 0x00000008
Note: A master operating in fast mode can operate with a slave in standard mode(< 100 Kb/s). But
in this case, the master should be programmed in standard mode to generate the
appropriate bit-rate.
Theoretically the minimum input clock frequency for the I²C
• If the I
2
C is in standard mode at 100 kHz is 1.4 MHz
• If the I
2
C is in fast mode at 400 kHz is 7.2 MHz.
I
2
C baud-rate counter register (I2C_BRCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED BRCNT2
R/W R/W
Description:
[31:16] RESERVED
[15:0] BRCNT2: baud rate counter 2. BRCNT2 defines the counter value used to
setup the I
2
C baud rate in standard and fast mode, when the peripheral is
operating in master mode, as described in :
Equation 2
Baud rate (fast) = fi2cclk / ((BRCNT2x3) + Foncycle)
Baud rate (standard) = fi2cclk / ((BRCNT2 x 2) + Foncycle)
The Foncycle means the delay between the SCL/SDA bus and the internal
SCL/SDA (i.e the SCL/SDA after filtering).
I2C_CR:FON = “00” => filter the clock spike wide = 0 => foncycle = 1
I2C_CR:FON = “01” => filter the clock spike wide = 1 => foncycle = 3
I2C_CR:FON = “10” => filter the clock spike wide = 2 => foncycle = 4
I2C_CR:FON = “11” => filter the clock spike wide = 4 => foncycle = 6