Datasheet

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C bus interface RM0352
84/138 DocID024647 Rev 1
10.2.7 I
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C transmit FIFO threshold register (I2C_TFTR)
Table 77. I
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C transmit FIFO threshold register (I2C_TFTR)
10.2.8 I
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C receive FIFO threshold register (I2C_RFTR)
Table 78. I
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C receive FIFO threshold register (I2C_RFTR)
Address: I2CBaseAddress + 0x20
Type: R/W
Reset: 0x00000000
Description: I
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C receive FIFO threshold register
I
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C transmit FIFO threshold register (I2C_TFTR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED THRESHOLD_TX
RR/W
Address: I2CBaseAddress + 0x1C
Type: R/W
Reset: 0x00000000
Description:
I
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C transmit FIFO threshold register
[9:0] THRESHOLD_TX: threshold Tx. THRESHOLD_TX contains the threshold
value, in terms of number of bytes, of the Tx FIFO.
When the number of entries of the Tx FIFO is less or equal than the threshold
value, the interrupt bit I2C_RISR:TXFNE is set in order to request the loading
of data to the application (in CPU mode).
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C receive FIFO threshold register (I2C_RFTR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED THRESHOLD_RX
RR/W
[9:0] THRESHOLD_RX: threshold Rx. THRESHOLD_RX contains the threshold
value, in terms of number of bytes, of the Rx FIFO.
When the number of entries of the Rx FIFO is greater or equal than the
threshold value, the interrupt bit I2C_RISR:RXFNF is set in order to request
the download of received data to the application. The application (in CPU
mode) shall download the received data based on threshold
(I2C_RISR:RXFNF).