Datasheet

I
2
C bus interface RM0352
80/138 DocID024647 Rev 1
10.2.5 I
2
C status register (I2C_SR)
Table 75. I
2
C status register (I2C_SR)
Address: I2CBaseAddress + 0x14
Type: R
Reset: 0x00000000
I
2
C status register (I2C_SR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
12
11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
DUALF
PECR
SMBDEFAULT
LENGTH
TYPE
CAUSE
STATUS
OP
RR R R R R R R R
Description: The status code word includes the status of the transfer in terms of:
• Operation type (master-read, master-write, write-to-slave, read-from-
slave)
• Status (successfully, abort)
• Cause of the abort occurrence
• Type (standard frame, general call, hardware general call)
• Length of the transaction (in terms of byte number).
• In SMBUS mode:
– SMBus device default address
– Packet error checking register
– Dual addressing flag
On the completion of a master or slave operation, the interrupt bit
I2C_RISR:MTD or I2C_RISR:STD is asserted and the related status of the
operation is stored in the current register.
[29] DUALF: dual flag (slave mode)
0: received address matched with the “Slave Address” (SA7)
1: received address matched with “Dual Slave Address” (DSA7)
• Cleared by hardware after a STOP condition or repeated START
condition, bus error or when
PE = 0.
[28:21] PECR: packet error checking register
This register contains the actual PEC calculated by hardware CRC-8 when
I2C_CR: ENPEC = 1.