Datasheet

DocID024647 Rev 1 79/138
RM0352 I
2
C bus interface
137
10.2.4 I
2
C transmit FIFO register (I2C_TFR)
Table 74. I
2
C transmit FIFO register (I2C_TFR)
Address: I2CBaseAddress + 0x10
Type: W
Reset: 0x00000000
[10:8] EA10: extended address. Includes the extension (MSB bits) of the field A7
used to initiate the current transaction.Valid only when the addressing mode
is set to 10 bits (AM = 10)
[7:1] A7: Address. Includes the 7-bit address or the LSB bits of the10-bit address
used to initiate the current transaction.
[0] OP: operation
0: indicates a master write operation
1: indicates a master read operation
I
2
C transmit FIFO register (I2C_TFR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TDATA
RW
Description: I
2
C transmit FIFO register
TDATA: transmission data. TDATA contains the payload related to a master
write or read- from-slave operation to be written in the Tx FIFO. The
TDATA(0) is the first LSB bit transmitted over the I
2
C line. In case of master
write operation, the Tx FIFO shall be preloaded otherwise the I
2
C controller
cannot start the operation until data are available.
[7:0]
In case of read-from-slave operation, when the slave is addressed, the
interrupt I2C_RISR:RFSR bit is asserted and the CPU shall download the
data in the FIFO. If the FIFO is empty and the I
2
C master is still requiring data,
a new request (I2C_RISR: RFSE interrupt bit) is asserted to require additional
data to the CPU. The slave controller stretches the I
2
C clock line when no
data are available for transmission. Since the Tx FIFO could contain some
pending data related to the previous transfer (the transfer length may be
unknown to the slave controller), the Tx FIFO is self-flushed before to assert
the I2C_RISR:RFSR bit. On the completion of the read-from-slave operation
the interrupt bit I2C_RISR:STD is asserted and the related status of the
operation is stored in the I2C_SR register.
In CPU mode the FIFO management shall be based on the assertion of the
interrupt bit I2C_RISR:TXFNE, related to the nearly-empty threshold.