Datasheet

I
2
C bus interface RM0352
78/138 DocID024647 Rev 1
Description: The control code word defines the features of the transfer. A typical transfer is
defined from the following:
• START condition
• Start byte procedure (optional)
• Address (7- or 10-bit) and read/write bit
• Data transmission/reception.
The master operations (read or write) are performed sequentially once at a time (no queuing
mode). On the writing of the I2C_MCR register, the related operation is triggered. In case of
write operation, the Tx FIFO shall be preloaded otherwise the I
2
C controller cannot start the
operation. Each operation initiates by the START command and can terminate by the STOP
command (I
2
C line). When the operation is not terminated by the STOP command a
repeated START will follow on the next required operation, otherwise the I
2
C line stalls.
On completion of the master operation (read or write) the interrupt bit I2C_RISR:MTD is
asserted and the related status of the operation is stored in the I2C_SR register. In case of
failure on a write operation (the transaction is aborted) the application shall flush the Tx
FIFO, asserting the control bit I2C_CR:FTX.
In case of 10-bit addressing, a master read operation must be preceded by
a master write to the same slave, due to the partial slave addressing used in 10-bit read
operations.
I
2
C master control register
[31:26] RESERVED
[25:15] LENGTH: transaction length. Defines the length, in terms of number of bytes
to be transmitted MW or received MR. In case of write operation, the payload
is stored in the Tx FIFO. A transaction can be larger than the Tx FIFO size.In
case of read operation the length refers to the number of bytes to be received
before to generate a not-acknowledge response.
A transaction can be larger than the Rx FIFO size. The I
2
C clock line is
stretched low until the data in the Rx FIFO are consumed.
[14] P: STOP condition
0: the current transaction is not terminated by a STOP condition.
A repeated START condition is generated on the next operation which is
required to avoid to stall the I
2
C line.
1: the current transaction is terminated by a STOP condition.
[13:12] AM: address type
00: the transaction is initiated by a general call command. In this case the
fields OP, A7, EA10 are don't care.
01: the transaction is initiated by the 7-bit address included in the A7 field.
10: the transaction is initiated by the 10-bit address included in the EA10 and
A7 fields.
11: RESERVED
[11] SB: Extended address
0: the start byte procedure is not applied to the current transaction
1: the start byte procedure is prefixed to the current transaction