Datasheet

DocID024647 Rev 1 77/138
RM0352 I
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C bus interface
137
10.2.2 I
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C slave control register (I2C_SCR)
Table 72. I
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C slave control register (I2C_SCR)
Address: I2CBaseAddress + 0x04
Type: R/W
Reset: 0x000F0055
Description: I
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C slave control register
10.2.3 I
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C master control register (I2C_MCR)
Table 73. I
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C master control register (I2C_MCR)
Address: I2CBaseAddress + 0x0C
Type: R/W
Reset: 0x00000000
I
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C slave control register (I2C_SCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLSU RESERVED ESA10 SA7
R/W R R/W R/W
[31:16] SLSU: slave data setup time. SLSU defines the data setup time after SCL
clock stretching in terms of i2c_clk cycles. Data setup time is actually equal to
SLSU-1 clock cycles.
This value depends on the mode selected (standard/fast) and on i2c_clk
frequency. The needed setup time for the two modes are 250 ns and 100 ns
respectively. In the Brain device, the typical value for i2c_clk is 26.66 MHz. So
SLSU typical value should be 8 in standard mode and 4 in fast mode.
[9:7] ESA10: extended slave address 10-bit. ESA10 includes the extension (MSB
bits) to the SA7 register field in case of slave addressing mode set to 10-bit
(I2C_CR:SAM = 1)
[6:0] SA7: slave address 7-bit. SA7 includes the slave address 7-bit or the LSB bits
of the slave address 10-bit. The slave addressing mode is set according to the
I2C_CR:SAM setting.
I
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C master control register (I2C_MCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LENGTH P AM SB EA10 A7 OP
R R/W R/W R/W R/W R/W R/W R/W