Datasheet

DocID024647 Rev 1 75/138
RM0352 I
2
C bus interface
137
[9] RESERVED
FRX flushes the receive circuitry (FIFO, fsm). The configuration of the I
2
C
node (register setting) is not affected by the flushing operation. The flushing
operation is performed on modules working on different clock domains
(system and I
2
C clocks) and needs several system clock cycles before to be
completed. On the completion, the I
2
C node (internal logic) clears this bit. The
application must not access to the Rx FIFO during the flushing operation and
should poll on this bit waiting for the completion.
0: flush operation is completed (I
2
C controller clears the bit)
1: flush operation is started and in progress (set by application).
FRX: flush receive.
[8]
[7] FTX: flush transmit.
FTX flushes the transmit circuitry (FIFO, fsm). The configuration of the I
2
C
node (register setting) is not affected by the flushing operation. The flushing
operation is performed on modules working on different clock domains
(system and I
2
C clocks) and needs several system clock cycles before to be
completed. On the completion, the I
2
C node (internal logic) clears this bit. The
application must not access to the Tx FIFO during the flushing operation and
should poll on this bit waiting for the completion.
0: flush operation is completed (I
2
C controller clears the bit)
1: flush operation is started and in progress (set by application).
[6] SGCM: slave general call mode. SGCM defines the operating mode of the
slave controller when a general call is received. This setting does not affect
the hardware general call that is always managed in transparent mode.
0: transparent mode, the slave receiver recognizes the general call at any
action is taken by software after the decoding of the message included in the
Rx FIFO.
1: direct mode, the slave receiver recognizes the general call and executes
directly (without software intervention) the related actions. Only the status
code word is stored in the I2C_SR register for notification to the application.
[5:4] SM: Speed Mode. SM defines the speed mode related to the serial bit rate:
00: Standard mode (up to 100 K/s)
01: Fast mode (up to 400 K/s)
10: Reserved
11: Reserved.
[3] SAM: Slave Addressing Mode. SAM defines the slave addressing mode when
the peripheral works in slave or master/slave mode. The received address is
compared with the content of the register I2C_SCR.
0: 7-bit addressing mode
1: 10-bit addressing mode.