Datasheet

DocID024647 Rev 1 73/138
RM0352 I
2
C bus interface
137
10.2 I
2
C register descriptions
10.2.1 I
2
C control register (I2C_CR)
Table 71. I
2
C control register (I2C_CR)
Address: I2CBaseAddress + 0x00
Type: R/W
Reset: 0x00000002 for I2C1 and 0x00000000 for I2C2
Description: I
2
C control register
I
2
C control register (I2C_CR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
ENBTIMEOUT
FRC_STRTCH
FREQ NACK
ENPEC ENARP
SMBUS
FS
FON
LM
RESERVED RESERVED RESERVED
FRX
FTX
SGCM
SM
SAM
OM
PE
R R/WR/W R/W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/
W
R/
W
R/WR/WR/WR/WR/W R/W R/W R/W R/W
[27] ENBTIMEOUT: timeout enable (SMBUS mode) This bit is used to enable
timeout check.
• When setting this bit in slave mode: the interrupt TIMEOUT is triggered
and slave resets the communication and lines are released.
• When setting this bit in master mode: the interrupt TIMEOUT is triggered
and master generates STOP condition.
0: timeout disabled 1: timeout enabled
[26] FRC_STRTCH: clock stretching force (SMBUS mode)
This bit is used to force clock stretching in master and slave mode. Clock
stretching is started after ACK when:
1- I2C_SR: LENGTH = I2C_SMB_SCR: LENGTH AND
I2C_CR:FRC_STRTCH = '1'(master mode)
OR
2- I2C_SR: LENGTH = I2C_MCR: LENGTH AND I2C_CR: FRC_STRTCH =
'1' (slave mode)
0: clock stretching disabled 1: clock stretching forced