Datasheet

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C bus interface RM0352
72/138 DocID024647 Rev 1
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C Base +0x034 I2C_MISR
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C masked interrupt status register. See Section 10.2.12: I2C
masked interrupt status register (I2C_MISR) on page 92.
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C Base +0x038 I2C_ICR
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C interrupt set and clear register. See Section 10.2.13: I2C
interrupt clear register (I2C_ICR) on page 93.
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C Base + 0x03C
to 0x048
RESERVED RESERVED for test.
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C Base +0x04C I2C_THDDAT
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C hold time data. See Section 10.2.14: I2C hold time data
(I2C_THDDAT) on page 93.
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C Base +0x050 I2C_THDSTA_FST_STD
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C hold time START condition F/S. See Section 10.2.15: I2C hold
time START condition F/S (I2C_THDSTA_FST_STD) on page 94.
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C Base +0x054 RESERVED This register must not be written and must keep its reset value
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C Base +0x058 I2C_TSUSTA_FST_STD
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C setup time START condition F/S. See Section 10.2.16: I2C
setup time START condition F/S (I2C_TSUSTA_FST_STD) on
page 95.
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C Base +0x05C RESERVED RESERVED
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C Base +0x060 I2C_SMB_SCR
SMBUS slave control register. See Section 10.2.17: SMBUS
slave control register (I2C_SMB_SCR) on page 95.
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C Base +0xFE0 I2C_PeriphID0
Peripheral identification register bits 7:0. See Section 10.2.18: I2C
peripheral identification register 0 (I2C_PERIPHID0) on page 96.
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C Base +0xFE4 I2C_PeriphID1
Peripheral identification register bits 15:8. See Section 10.2.19:
I2C peripheral identification register 1 (I2C_PERIPHID1) on
page 96.
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C Base +0xFE8 I2C_PeriphID2
Peripheral identification register bits 23:16. See Section 10.2.20:
I2C peripheral identification register 2 (I2C_PERIPHID2) on
page 97.
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C Base +0xFEC I2C_PeriphID3
Peripheral identification register bits 31:24. See Section 10.2.21:
I2C peripheral identification register 3 (I2C_PERIPHID3) on
page 97.
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C Base +0xFF0 I2C_PCellID0
IPCell identification register bits 7:0. See Section 10.2.22: I2C
PCell identification register 0 (I2C_PCELLID0) on page 98.
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C Base +0xFF4 I2C_PCellID1
IPCell identification register bits 15:8. See Section 10.2.23: I2C
PCell identification register 1 (I2C_PCELLID1) on page 98.
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C Base +0xFF8 I2C_PCellID2
IPCell identification register bits 23:16. See Section 10.2.24: I2C
PCell identification register 2 (I2C_PCELLID2) on page 99.
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C Base +0xFFC I2C_PCellID3
IPCell identification register bits 31:24. See Section 10.2.25: I2C
PCell identification register 3 (I2C_PCELLID3) on page 99.
1. All the I
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C configuration registers (I2C_CR (excluded PE, FTX and FRX bits, etc.) can be modified only when the device is
disabled (I2C_CR:PE bit is reset) to avoid synchronization problems with the different clock domains (system, I
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C clocks).
Table 70. I
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C register list
(1)
(continued)
Address Name Description