Datasheet
DocID024647 Rev 1 71/138
RM0352 I
2
C bus interface
137
10 I
2
C bus interface
The Brain device provides two I
2
C bus interfaces that support following features:
• Slave transmitter/receiver and master transmitter/receiver
• 7- and 10-bit addressing
• Standard (100 KHz) and fast (400 KHz) speeds
• The transmit path is buffered in a 16-byte Tx FIFO and the receive paths is buffered in
a 16-byte Rx FIFO.
In addition to receiving and transmitting data, the interface converts data from serial to
parallel format and vice-versa using an interrupt or polled handshake. The interrupts are
enabled and disabled in software.
10.1 I
2
C registers
The base address of the I
2
C blocks in Brain memory map is 0xA400_0000 for I2C1 and
0xA500_0000 for I2C2.
Table 70. I
2
C register list
(1)
Address Name Description
I
2
C Base +0x000 I2C_CR
I
2
C control register. See Section 10.2.1: I2C control register
(I2C_CR) on page 73.
I
2
C Base +0x004 I2C_SCR
I
2
C slave control register. See Section 10.2.2: I2C slave control
register (I2C_SCR) on page 77.
I
2
C Base +0x008 RESERVED This register must not be written and must keep its reset value
I
2
C Base +0x00C I2C_MCR
I
2
C master control register. See Section 10.2.3: I2C master
control register (I2C_MCR) on page 77.
I
2
C Base +0x010 I2C_TFR
I
2
C transmit FIFO register. See Section 10.2.4: I2C transmit FIFO
register (I2C_TFR) on page 79.
I
2
C Base +0x014 I2C_SR
I
2
C status register. See Section 10.2.5: I2C status register
(I2C_SR) on page 80.
I
2
C Base +0x018 I2C_RFR
I
2
C receive FIFO register. See Section 10.2.6: I2C receive FIFO
register (I2C_RFR) on page 83.
I
2
C Base +0x01C I2C_TFTR
I
2
C transmit FIFO threshold register. See Section 10.2.7: I2C
transmit FIFO threshold register (I2C_TFTR) on page 84.
I
2
C Base +0x020 I2C_RFTR
I
2
C receive FIFO threshold register. See Section 10.2.8: I2C
receive FIFO threshold register (I2C_RFTR) on page 84.
I
2
C Base +0x024 RESERVED This register must not be written and must keep its reset value
I
2
C Base +0x028 I2C_BRCR
I
2
C baud rate counter register. See Section 10.2.9: I2C baud-rate
counter register (I2C_BRCR) on page 85.
I
2
C Base +0x02C I2C_IMSCR
I
2
C interrupt mask set and clear register. See Section 10.2.10:
I2C interrupt mask set/clear register (I2C_IMSCR) on page 86.
I
2
C Base +0x030 I2C_RISR
I
2
C raw interrupt status register. See Section 10.2.11: I2C raw
interrupt status register (I2C_RISR) on page 88.