Datasheet

DocID024647 Rev 1 65/138
RM0352 ARM
©
dual timer module (SP804)
137
Figure 14. PrimeCell identification register bit assignments
The four, 8-bit PrimeCell identification registers are described in the following subsections:
• PrimeCell ID0 register, TimerPCellID0
• PrimeCell ID1 register, TimerPCellID1
• PrimeCell ID2 register, TimerPCellID2
• PrimeCell ID3 register, TimerPCellID3
PrimeCell ID0 register, TimerPCellID0
The TimerPCellID0 register is hard-coded and the fields in the register determine the reset
value. Table 61 shows the bit assignments of the register.
PrimeCell ID1 register, TimerPCellID1
The TimerPCellID1 register is hard-coded and the fields in the register determine the reset
value. Table 62 shows the bit assignment of the register.
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Table 61. PrimeCell ID0 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:0] TimerPCellID0 These bits read back as 0x0D
Table 62. PrimeCell ID1 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:0] TimerPCellID1 These bits read back as 0xF0