Datasheet

ARM
©
dual timer module (SP804) RM0352
64/138 DocID024647 Rev 1
Timer peripheral ID1 register, TimerPeriphID1
The TimerPeriphID1 register is hard-coded and the fields in the register determine the reset
value.Table 58 lists the bit assignments of the register.
Timer peripheral ID2 register, TimerPeriphID2
The TimerPeriphID2 register is hard-coded and the fields in the register determine the reset
value. Table 59 lists the bit assignment of the register.
Timer peripheral ID3 register, TimerPeriphID3
The TimerPeriphID3 register is hard-coded and the fields in the register determine the reset
value. Table 60 shows the bit assignments of the register.
PrimeCell identification registers, TimerPCellID0-3
The TimerPCellID0-3 registers are four 8-bit registers, that span address locations 0xFF0-
0xFFC. The read-only registers can conceptually be treated as a 32-bit register. The register
is used as a standard cross-peripheral identification system. The TimerPCellID register is
set to 0xB105F00D. Figure 14 shows the bit assignment for the registers.
Table 58. Timer peripheral ID1 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:4] Designer0 These bits read back as 0x1
[3:0] PartNumber1 These bits read back as 0x8
Table 59. Timer peripheral ID2 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:4] Revision These bits read back as 0x1
[3:0] Designer1 These bits read back as 0x4
Table 60. TimerPeriphID3 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:0] Configuration These bits read back as 0x00