Datasheet

DocID024647 Rev 1 59/138
RM0352 ARM
©
dual timer module (SP804)
137
8.3.2 Register descriptions
This section describes the dual timer module registers:
• Load register, TimerXLoad
• Current value register, TimerXValue
• Control register, TimerXControl
• Interrupt clear register. TimerXIntClr
• Raw interrupt status register, TimerXRIS
• Masked interrupt status register, TimerXMIS
• Background load register, TimerXBGLoad
• Peripheral identification registers, TimerPeriphID0-3
• PrimeCell identification registers, TimerPCellID0-3
Note: The letter X used in register names means a register in either FRC1 or FRC2.
Base+0x38 Read/write 32 0x00000000 Timer2BGLoad
See Section : Background load register,
TimerXBGLoad on page 62
Base+0x40-
0xEFC
- - - - RESERVED for future expansion
Base+0xF00-
0xF04
- - - - RESERVED for test
Base+0xF08-
0xFDC
- - - - RESERVED for future expansion
Base+0xFE0 Read-only 8 0x04 TimerPeriphID0
See Section : Timer peripheral ID0
register, TimerPeriphID0 on page 63
Base+0xFE4 Read-only 8 0x18 TimerPeriphID1
See Section : Timer peripheral ID1
register, TimerPeriphID1 on page 64
Base+0xFE8 Read-only 8 0x14 TimerPeriphID2
See Section : Timer peripheral ID2
register, TimerPeriphID2 on page 64
Base+0xFEC Read-only 8 0x00 TimerPeriphID3
See Section : Timer peripheral ID3
register, TimerPeriphID3 on page 64
Base+0xFF0 Read-only 8 0x0D TimerPCellID0
See Section : PrimeCell ID0 register,
TimerPCellID0 on page 65
Base+0xFF4 Read-only 8 0xF0 TimerPCellID1
See Section : PrimeCell ID1 register,
TimerPCellID1 on page 65
Base+0xFF8 Read-only 8 0x05 TimerPCellID2
See Section : PrimeCell ID2 register,
TimerPCellID2 on page 66
Base+0xFFC Read-only 8 0xB1 TimerPCellID3
See Section : PrimeCell ID3 register,
TimerPCellID3 on page 66
Table 52. Summary of registers (continued)
Address Type Width Reset value Name Description