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ManualsBrandsARM ManualsComputer HardwareCortex r1p3
51525354555657585960
ARM
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dual timer module (SP804) RM0352
56/138 DocID024647 Rev 1
Figure 11 illustrates an example of the timing for an interrupt being raised and cleared.
Figure 11. Example interrupt signal timing
The interrupt signals generated by the timer module, TIMINT1 and TIMINT2, can be
masked by setting the IntEnable bit to 0 in the TimerXControl register. The raw interrupt
status prior to masking can be read from the TimerXRIS register and the masked interrupt
status can be read from the TimerXMIS register. Figure 12 shows how the raw and masked
interrupt status is accessed.
Figure 12. Raw and masked interrupt status
Programming the timer interval
Table 51 shows the equations that are used to calculate the timer interval generated for
each timer mode in terms of:
• TIMCLKFREQ is the frequency of TIMCLK.15
• TIMCLKENXDIV is the effective division of the TIMCLK rate by the clock enable,
TIMCLKENX. For example, if TIMCLKENX enables every fourth TIMCLK edge then
TIMCLKENXDIV = 4.
• PRESCALEDIV is the prescaler division factor of 1, 16, or 256. Derived from
• Control register bits [3:2].
• TimerXLoad is the value in the load register.