Datasheet

DocID024647 Rev 1 55/138
RM0352 ARM
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dual timer module (SP804)
137
new load value and uses this new load value for each subsequent reload for as long as the
timer is enabled in periodic mode.
If the counter is disabled by clearing the TimerEn bit in the TimerControl register, the counter
halts and holds its current value. If the counter is re-enabled again then the counter
continues decrementing from the current value.
One-shot mode
One-shot timer mode is selected by setting the OneShot bit in the TimerControl register to 1.
The TimerMode bit has no effect in one-shot mode.
The 32-bit or 16-bit counter operation is selected by setting the TimerSize bit appropriately
in the TimerControl register.
To initiate a count down sequence in one-shot mode, write a new load value to the
TimerXLoad register and the counter starts decrementing from this value if enabled.
In 32-bit mode, the full 32-bits of the counter are decremented and when the count reaches
zero, 0x00000000, an interrupt is generated and the counter halts.
In 16-bit mode, only the least significant 16-bits of the counter are decremented and when
the count reaches 0x0000, an interrupt is generated and the counter halts.
One-shot mode can be retriggered by writing a new value to the TimerXLoad register. The
counter values change to the new load value on the next TIMCLK when TIMCLKENX is
HIGH.
Interrupt behavior
An interrupt is generated if IntEnable = 1 and the counter reaches 0x00000000 in 32-bit
mode or 0xXXXX0000 in 16-bit mode. The most significant 16 bits of the counter are
ignored in 16-bit mode.
When the Timer module raises an interrupt by asserting TIMINTX, the timing of this signal is
generated from a rising clock edge of TIMCLK enabled by TIMCLKENX. When the interrupt
is cleared by a write to the interrupt clear register, TimerXIntClr, the TIMINTX signal is
deasserted immediately in the PCLK domain rather than waiting for the next enabled
TIMCLK rising edge.