Datasheet

DocID024647 Rev 1 49/138
RM0352 ARM
©
dual timer module (SP804)
137
The dual timer module consists of two identical programmable “Free Running Counters”
(FRCs) that can be configured for 32-bit or 16-bit operation and one of three timer modes:
• Free running
• Periodic
• One-shot.
The FRCs operate from a common timer clock, TIMCLK with each FRC having its own clock
enable input, TIMCLKEN1 and TIMCLKEN2. Each FRC also has a prescaler that can divide
down the enabled TIMCLK rate by 1, 16, or 256. This enables the count rate for each FRC
to be controlled independently using their individual clock enables and prescalers.
TIMCLK can be equal to or be a submultiple of the PCLK frequency. However, the positive
edges of TIMCLK and PCLK must be synchronous and balanced.
The operation of each Timer module is identical. A Timer module can be programmed for
a 32-bit or 16-bit counter size and one of three timer modes using the control register. The
three timer modes are:
Free running The counter operates continuously and wraps around to its maximum
value each time that it reaches zero.
Periodic The counter operates continuously by reloading from the load register
each time that the counter reaches zero.
One-shot The counter is loaded with a new value by writing to the load register.
The counter decrements to zero and then halts until it is reprogrammed.
The timer count is loaded by writing to the load register and, if enabled, the timer count
decrements at a rate determined by TIMCLK, TIMCLKENX, and the prescaler setting. When
the Timer counter is already running, writing to the load register causes the counter to
immediately restart from the new value.
An alternative way of loading the Timer count is by writing to the background load register.
This has no immediate effect on the current count but the counter continues to decrement.
On reaching zero, the Timer count is reloaded from the new load value if it is in periodic
mode.
When the Timer count reaches zero an interrupt is generated. The interrupt is cleared by
writing to the interrupt clear register. The external interrupt signals can be masked off by the
interrupt mask registers.
The current counter value can be read from the value register at any time.