Datasheet

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RM0352 ARM
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dual timer module (SP804)
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8 ARM
©
dual timer module (SP804)
This section is intended for hardware and software engineers implementing “System-on-
Chip” (SoC) designs.
The SP804 timer is an IP provided by ARM (SP804). Additional details about its functional
blocks may be found in “ARM Dual-Timer module (SP804) Technical Reference Manual”.
8.1 Introduction
This section introduces the dual timer module (SP804). It contains the following parts:
• About the ARM dual timer module (SP804)
• Features
• Programmable parameters
8.1.1 About the ARM dual timer module (SP804)
The ARM dual timer module is an “Advanced Microcontroller Bus Architecture” (AMBA)
compliant system-on-chip (SoC) peripheral developed, tested and licensed by ARM Limited.
The module is an AMBA slave module and connects to the “Advanced Peripheral Bus”
(APB). The dual timer module consists of two programmable 32/16-bit down counters that
can generate interrupts on reaching zero.
8.1.2 Features
The features of the dual timer module are:
• Compliance to the AMBA Specification (Rev 2.0) for easy integration into SoC
implementation.
• Two 32/16-bit down counters with free running, periodic and one-shot modes.
• Common clock with separate clock-enables for each timer gives flexible control of the
timer intervals.
• Interrupt output generation on timer count reaching zero.
• Identification registers that uniquely identify the dual timer module. These can be used
by software to automatically configure itself.