Datasheet

DocID024647 Rev 1 45/138
RM0352 Watchdog timer (WDG)
137
Table 42. Watchdog peripheral identification register WDTPeriphID0-3 - part 2
Table 43. Watchdog peripheral identification register WDTPeriphID0-3 - part 3
Table 44. Watchdog peripheral identification register WDTPeriphID0-3 - part 4
7.2.9 Watchdog PCell identification register WDTPCellID0-3
The WDTPCellID0-3 registers are four 8-bit registers that span the address location 0xFF0
to 0xFFC. The registers are read-only.
Table 46. Watchdog PCell identification register WDTPCellID0-3 - part 1
WDTPeriphID1 (WDT Base + 0xFE4) Reset value: 0x0000_0018
31 30 29 28 27 26 25 24 2322 21 20 19 18 17 16 15 14 13 12 11 10 9876543 2 1 0
RESERVED Designer0 Part number1
RRR
WDTPeriphID2 (WDT Base + 0xFE8) Reset value: 0x0000_0004
31 30 29 28 27 26 25 24 2322 21 20 19 18 17 16 15 14 13 12 11 10 9876543 2 1 0
RESERVED Revision Designer1
RRR
WDTPeriphID3 (WDT Base + 0xFEC) Reset value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Configuration
RR
Table 45. WDTPeriphID0-3 register bit fields
Bit field Function
PartNumber0 These bits read back as 0x05
PartNumber1 These bits read back as 0x8
Designer0 These bits read back as 0x1
Designer1 These bits read back as 0x4
Revision These bits read back as 0x0
Configuration These bits read back as 0x00
WDTPCellID0 (WDT Base + 0xFF0) Reset value: 0x0000_000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED WDTPCellID0
RR