Datasheet

Watchdog timer (WDG) RM0352
42/138 DocID024647 Rev 1
7.2.3 Watchdog control register WDT_CR
The WDT_CR register allows configuring the watchdog timer. The bit assignment is listed in
Table 32.
Table 31. Watchdog control register WDT_CR
7.2.4 Watchdog interrupt clear register WDT_ICR
Writing any value to this register will clear the interrupt output from the watchdog, and
reloads the counter from the value in the WDT_LR register.
Table 33. Watchdog interrupt clear register WDT_ICR
WDT_CR (WDT Base + 0x008) Reset value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESEN INTEN
RR/WR/W
Table 32. WDT_CR register bit fields
Bit field Function
RESEN
Watchdog reset enable
Enable watchdog reset output (WDOGRES). Acts as a mask for the reset out- put.
0b: watchdog reset disabled (default).
1b: watchdog reset enabled.
INTEN
Watchdog interrupt enable
Enable the interrupt event (WDOGINT):
0b: watchdog interrupt disabled (default).
1b: watchdog interrupt enabled.
WDT_ICR (WDT Base + 0x00C) Reset value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDT_ICLR
W
Table 34. WDT_ICR register bit fields
Bit Field Function
WDT_ICLR
Watchdog interrupt clear
Writing any value will clear the watchdog interrupt and reloads the counter from the WDT_LR
register.
Reading returns zero.